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1e94b46f73
This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
261 lines
6.5 KiB
C
261 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2012 SAMSUNG Electronics
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* Jaehoon Chung <jh80.chung@samsung.com>
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*/
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#include <common.h>
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#include <dwmmc.h>
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#include <fdtdec.h>
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#include <asm/global_data.h>
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#include <linux/libfdt.h>
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#include <malloc.h>
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#include <errno.h>
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#include <asm/arch/dwmmc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/power.h>
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#include <asm/gpio.h>
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#include <linux/printk.h>
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#define DWMMC_MAX_CH_NUM 4
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#define DWMMC_MAX_FREQ 52000000
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#define DWMMC_MIN_FREQ 400000
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#define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001
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#define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001
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#ifdef CONFIG_DM_MMC
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#include <dm.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct exynos_mmc_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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#endif
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/* Exynos implmentation specific drver private data */
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struct dwmci_exynos_priv_data {
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#ifdef CONFIG_DM_MMC
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struct dwmci_host host;
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#endif
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u32 sdr_timing;
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};
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/*
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* Function used as callback function to initialise the
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* CLKSEL register for every mmc channel.
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*/
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static int exynos_dwmci_clksel(struct dwmci_host *host)
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{
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#ifdef CONFIG_DM_MMC
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struct dwmci_exynos_priv_data *priv =
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container_of(host, struct dwmci_exynos_priv_data, host);
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#else
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struct dwmci_exynos_priv_data *priv = host->priv;
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#endif
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dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
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return 0;
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}
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unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
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{
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unsigned long sclk;
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int8_t clk_div;
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/*
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* Since SDCLKIN is divided inside controller by the DIVRATIO
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* value set in the CLKSEL register, we need to use the same output
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* clock value to calculate the CLKDIV value.
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* as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
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*/
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clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
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& DWMCI_DIVRATIO_MASK) + 1;
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sclk = get_mmc_clk(host->dev_index);
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/*
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* Assume to know divider value.
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* When clock unit is broken, need to set "host->div"
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*/
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return sclk / clk_div / (host->div + 1);
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}
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static void exynos_dwmci_board_init(struct dwmci_host *host)
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{
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struct dwmci_exynos_priv_data *priv = host->priv;
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if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
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dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
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dwmci_writel(host, EMMCP_SEND0, 0);
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dwmci_writel(host, EMMCP_CTRL0,
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MPSCTRL_SECURE_READ_BIT |
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MPSCTRL_SECURE_WRITE_BIT |
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MPSCTRL_NON_SECURE_READ_BIT |
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MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
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}
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/* Set to timing value at initial time */
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if (priv->sdr_timing)
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exynos_dwmci_clksel(host);
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}
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static int exynos_dwmci_core_init(struct dwmci_host *host)
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{
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unsigned int div;
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unsigned long freq, sclk;
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if (host->bus_hz)
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freq = host->bus_hz;
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else
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freq = DWMMC_MAX_FREQ;
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/* request mmc clock vlaue of 52MHz. */
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sclk = get_mmc_clk(host->dev_index);
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div = DIV_ROUND_UP(sclk, freq);
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/* set the clock divisor for mmc */
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set_mmc_clk(host->dev_index, div);
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host->name = "EXYNOS DWMMC";
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#ifdef CONFIG_EXYNOS5420
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host->quirks = DWMCI_QUIRK_DISABLE_SMU;
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#endif
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host->board_init = exynos_dwmci_board_init;
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host->caps = MMC_MODE_DDR_52MHz;
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host->clksel = exynos_dwmci_clksel;
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host->get_mmc_clk = exynos_dwmci_get_clk;
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#ifndef CONFIG_DM_MMC
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/* Add the mmc channel to be registered with mmc core */
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if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
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printf("DWMMC%d registration failed\n", host->dev_index);
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return -1;
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}
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#endif
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return 0;
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}
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static int do_dwmci_init(struct dwmci_host *host)
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{
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int flag, err;
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flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
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err = exynos_pinmux_config(host->dev_id, flag);
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if (err) {
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printf("DWMMC%d not configure\n", host->dev_index);
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return err;
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}
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return exynos_dwmci_core_init(host);
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}
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static int exynos_dwmci_get_config(const void *blob, int node,
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struct dwmci_host *host,
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struct dwmci_exynos_priv_data *priv)
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{
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int err = 0;
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u32 base, timing[3];
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/* Extract device id for each mmc channel */
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host->dev_id = pinmux_decode_periph_id(blob, node);
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host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
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if (host->dev_index == host->dev_id)
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host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
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if (host->dev_index > 4) {
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printf("DWMMC%d: Can't get the dev index\n", host->dev_index);
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return -EINVAL;
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}
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/* Get the bus width from the device node (Default is 4bit buswidth) */
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host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4);
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/* Set the base address from the device node */
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base = fdtdec_get_addr(blob, node, "reg");
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if (!base) {
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printf("DWMMC%d: Can't get base address\n", host->dev_index);
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return -EINVAL;
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}
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host->ioaddr = (void *)base;
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/* Extract the timing info from the node */
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err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
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if (err) {
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printf("DWMMC%d: Can't get sdr-timings for devider\n",
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host->dev_index);
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return -EINVAL;
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}
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priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
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DWMCI_SET_DRV_CLK(timing[1]) |
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DWMCI_SET_DIV_RATIO(timing[2]));
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/* sdr_timing didn't assigned anything, use the default value */
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if (!priv->sdr_timing) {
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if (host->dev_index == 0)
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priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
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else if (host->dev_index == 2)
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priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
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}
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host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
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host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
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host->div = fdtdec_get_int(blob, node, "div", 0);
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return 0;
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}
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#ifdef CONFIG_DM_MMC
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static int exynos_dwmmc_probe(struct udevice *dev)
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{
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struct exynos_mmc_plat *plat = dev_get_plat(dev);
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct dwmci_exynos_priv_data *priv = dev_get_priv(dev);
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struct dwmci_host *host = &priv->host;
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int err;
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err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host,
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priv);
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if (err)
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return err;
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err = do_dwmci_init(host);
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if (err)
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return err;
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dwmci_setup_cfg(&plat->cfg, host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ);
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host->mmc = &plat->mmc;
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host->mmc->priv = &priv->host;
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host->priv = dev;
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upriv->mmc = host->mmc;
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return dwmci_probe(dev);
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}
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static int exynos_dwmmc_bind(struct udevice *dev)
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{
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struct exynos_mmc_plat *plat = dev_get_plat(dev);
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return dwmci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id exynos_dwmmc_ids[] = {
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{ .compatible = "samsung,exynos4412-dw-mshc" },
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{ .compatible = "samsung,exynos-dwmmc" },
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{ }
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};
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U_BOOT_DRIVER(exynos_dwmmc_drv) = {
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.name = "exynos_dwmmc",
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.id = UCLASS_MMC,
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.of_match = exynos_dwmmc_ids,
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.bind = exynos_dwmmc_bind,
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.ops = &dm_dwmci_ops,
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.probe = exynos_dwmmc_probe,
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.priv_auto = sizeof(struct dwmci_exynos_priv_data),
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.plat_auto = sizeof(struct exynos_mmc_plat),
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};
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#endif
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