mirror of
https://github.com/u-boot/u-boot.git
synced 2024-12-05 02:23:31 +08:00
587c3f8ebe
The problem is that timeout bits in WCR register were leaved unchanged. So previously set timeout value was applied and therefore 'reset' command takes any value up to two minutes, depending on previous watchdog settings, instead of minimal 0.5 seconds. Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com> |
||
---|---|---|
.. | ||
at91sam9_wdt.c | ||
bfin_wdt.c | ||
designware_wdt.c | ||
ftwdt010_wdt.c | ||
imx_watchdog.c | ||
Kconfig | ||
Makefile | ||
omap_wdt.c | ||
s5p_wdt.c | ||
xilinx_tb_wdt.c |