Eugeniy Paltsev 95336738f1 ARC: Cache: Fix SLC operations when SLC is bypassed for data ... If L1 D$ is disabled SLC is bypassed for data and all load/store requests are sent directly to main memory. If L1 I$ is disabled SLC is NOT bypassed for instructions and all instruction requests are fetched through SLC. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>		2018-03-21 17:06:54 +03:00
..
cpu	arc: No need in sections defined in sources with newer tools	2016-08-05 12:50:25 +03:00
dts	ARC: HSDK: DTS: Add cgu-clk node	2018-01-19 17:59:35 +03:00
include/asm	ARC: Move IOC enabling to compile-time options	2018-03-21 17:06:54 +03:00
lib	ARC: Cache: Fix SLC operations when SLC is bypassed for data	2018-03-21 17:06:54 +03:00
config.mk	arc: Eliminate unused code and data with GCC's garbage collector	2018-03-21 16:21:34 +03:00
Kconfig	ARC: Move IOC enabling to compile-time options	2018-03-21 17:06:54 +03:00
Makefile	arc: introduce separate section for interrupt vector table	2015-01-15 22:38:42 +03:00