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https://github.com/u-boot/u-boot.git
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c837dcb1a3
before we can access it; add delay in case we are faster (with no CF card inserted) * Cleanup of some init functions * Make sure SCC Ethernet is always stopped by the time we boot Linux to avoid Linux crashes by early packets coming in. * Accelerate flash accesses on LWMON board by using buffered writes
361 lines
13 KiB
C
361 lines
13 KiB
C
/*
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* (C) Copyright 2000
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* Murray Jensen <Murray.Jensen@cmst.csiro.au>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Config header file for Cogent platform using an MPC8xx CPU module
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC860 1 /* This is an MPC860 CPU */
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#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
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#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
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/* Cogent Modular Architecture options */
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#define CONFIG_CMA286_60_OLD 1 /* ...on an old CMA286-60 CPU module */
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#define CONFIG_CMA102 1 /* ...on a CMA102 motherboard */
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#define CONFIG_CMA302 1 /* ...with a CMA302 flash I/O module */
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/* serial console configuration */
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#undef CONFIG_8xx_CONS_SMC1
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#undef CONFIG_8xx_CONS_SMC2
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#define CONFIG_8xx_CONS_NONE /* not on 8xx serial ports (eg on cogent m/b) */
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#if defined(CONFIG_CMA286_60_OLD)
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#define CONFIG_8xx_GCLK_FREQ 33333000 /* define if cant use get_gclk_freq */
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#endif
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#define CONFIG_BAUDRATE 230400
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_KGDB | CFG_CMD_I2C) & ~CFG_CMD_NET)
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/
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#define CONFIG_BOOTARGS "root=/dev/ram rw"
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
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#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
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#define CONFIG_KGDB_NONE /* define if kgdb on something else */
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#define CONFIG_KGDB_INDEX 2 /* which SMC/SCC channel for kgdb */
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#endif
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#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#define CFG_ALLOC_DPRAM
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Low Level Cogent settings
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* if CFG_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
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* also, make sure CONFIG_CONS_INDEX is still defined - the index will be
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* 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
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* (second 2 for CMA120 only)
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*/
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#define CFG_CMA_MB_BASE 0x00000000 /* base of m/b address space */
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#include <configs/cogent_common.h>
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#define CFG_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
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#define CONFIG_CONS_INDEX 1
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#define CFG_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
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#define CONFIG_SHOW_ACTIVITY
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#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
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/*
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* flash exists on the motherboard
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* set these four according to TOP dipsw:
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* TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low )
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* TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high)
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*/
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#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE
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#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE
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#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE
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#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE
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#endif
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#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE
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#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xFF000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE CMA_MB_RAM_BASE
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#ifdef CONFIG_CMA302
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#define CFG_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
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#else
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#define CFG_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
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#endif
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR CFG_FLASH_BASE /* Addr of Environment Sector */
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#ifdef CONFIG_CMA302
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#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
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#define CFG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */
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#else
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif /* CONFIG_WATCHDOG */
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit - leave PLL multiplication factor unchanged !
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*/
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#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00)
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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*-----------------------------------------------------------------------
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*
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*/
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#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
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#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
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#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
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#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_IO_ADDR (0xEC000000)
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#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
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/*#define CFG_DER 0x2002000F*/
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#define CFG_DER 0
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#if defined(CONFIG_CMA286_60_OLD)
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/*
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* Init Memory Controller:
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*
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* NOTE: although the names (CFG_xRn_PRELIM) suggest preliminary settings,
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* they are actually the final settings for this cpu/board, because the
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* flash and RAM are on the motherboard, accessed via the CMAbus, and the
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* mappings are pretty much fixed.
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*
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* (the *_SIZE vars must be a power of 2)
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*/
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#define CFG_CMA_CS0_BASE TEXT_BASE /* EPROM */
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#define CFG_CMA_CS0_SIZE (1 << 20)
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#define CFG_CMA_CS1_BASE CMA_MB_RAM_BASE /* RAM + I/O SLOT 1 */
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#define CFG_CMA_CS1_SIZE (64 << 20)
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#define CFG_CMA_CS2_BASE CMA_MB_SLOT2_BASE /* I/O SLOTS 2 + 3 */
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#define CFG_CMA_CS2_SIZE (64 << 20)
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#define CFG_CMA_CS3_BASE CMA_MB_ROMLOW_BASE /* M/B I/O */
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#define CFG_CMA_CS3_SIZE (32 << 20)
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/*
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* CS0 maps the EPROM on the cpu module
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* Set it for 4 wait states, address CFG_MONITOR_BASE and size 1M
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*
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* Note: We must have already transferred control to the final location
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* of the EPROM before these are used, because when BR0/OR0 are set, the
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* mirror of the eprom at any other addresses will disappear.
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*/
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/* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
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#define CFG_BR0_PRELIM ((CFG_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V)
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/* mask size CFG_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
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#define CFG_OR0_PRELIM ((~(CFG_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK)
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/*
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* CS1 maps motherboard DRAM and motherboard I/O slot 1
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* (each 32Mbyte in size)
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*/
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/* base address = CFG_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
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#define CFG_BR1_PRELIM ((CFG_CMA_CS1_BASE&BR_BA_MSK)|BR_V)
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/* mask size CFG_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
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#define CFG_OR1_PRELIM ((~(CFG_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA)
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/*
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* CS2 maps motherboard I/O slots 2 and 3
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* (each 32Mbyte in size)
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*/
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/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
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#define CFG_BR2_PRELIM ((CFG_CMA_CS2_BASE&BR_BA_MSK)|BR_V)
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/* mask size CFG_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
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#define CFG_OR2_PRELIM ((~(CFG_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA)
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/*
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* CS3 maps motherboard I/O
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* (32Mbyte in size)
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*/
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/* base address = CFG_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
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#define CFG_BR3_PRELIM ((CFG_CMA_CS3_BASE&BR_BA_MSK)|BR_V)
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/* mask size CFG_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
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#define CFG_OR3_PRELIM ((~(CFG_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA)
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#endif
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#endif /* __CONFIG_H */
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