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93145335fb
The way that we use this file currently means that we have to guard it in every platform Kconfig. But it is also required in all NXP platforms, including non-reference platforms. Make all options in it have appropriate dependencies so that we can include it a single time under arch/Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
478 lines
11 KiB
Plaintext
478 lines
11 KiB
Plaintext
config ARCH_MAP_SYSMEM
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depends on SANDBOX
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def_bool y
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config CREATE_ARCH_SYMLINK
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bool
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config HAVE_ARCH_IOREMAP
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bool
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config SYS_CACHE_SHIFT_4
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bool
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config SYS_CACHE_SHIFT_5
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bool
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config SYS_CACHE_SHIFT_6
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bool
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config SYS_CACHE_SHIFT_7
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bool
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config SYS_CACHELINE_SIZE
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int
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default 128 if SYS_CACHE_SHIFT_7
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default 64 if SYS_CACHE_SHIFT_6
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default 32 if SYS_CACHE_SHIFT_5
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default 16 if SYS_CACHE_SHIFT_4
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# Fall-back for MIPS
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default 32 if MIPS
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config LINKER_LIST_ALIGN
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int
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default 32 if SANDBOX
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default 8 if ARM64 || X86
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default 4
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help
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Force the each linker list to be aligned to this boundary. This
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is required if ll_entry_get() is used, since otherwise the linker
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may add padding into the table, thus breaking it.
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See linker_lists.rst for full details.
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choice
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prompt "Architecture select"
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default SANDBOX
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config ARC
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bool "ARC architecture"
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select ARC_TIMER
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select CLK
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select DM
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select HAVE_PRIVATE_LIBGCC
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select SUPPORT_OF_CONTROL
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select SYS_CACHE_SHIFT_7
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select TIMER
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config ARM
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bool "ARM architecture"
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select ARCH_SUPPORTS_LTO
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select CREATE_ARCH_SYMLINK
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select HAVE_PRIVATE_LIBGCC if !ARM64
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select SUPPORT_ACPI
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select SUPPORT_OF_CONTROL
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config M68K
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bool "M68000 architecture"
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select HAVE_PRIVATE_LIBGCC
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select NEEDS_MANUAL_RELOC
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select SYS_BOOT_GET_CMDLINE
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select SYS_BOOT_GET_KBD
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select SYS_CACHE_SHIFT_4
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select SUPPORT_OF_CONTROL
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config MICROBLAZE
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bool "MicroBlaze architecture"
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select SUPPORT_OF_CONTROL
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imply CMD_TIMER
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imply SPL_REGMAP if SPL
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imply SPL_TIMER if SPL
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imply TIMER
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imply XILINX_TIMER
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config MIPS
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bool "MIPS architecture"
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select HAVE_ARCH_IOREMAP
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select HAVE_PRIVATE_LIBGCC
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select SUPPORT_OF_CONTROL
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select SPL_SEPARATE_BSS if SPL
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config NIOS2
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bool "Nios II architecture"
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select CPU
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select DM
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imply DM_EVENT
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select OF_CONTROL
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select SUPPORT_OF_CONTROL
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imply CMD_DM
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config PPC
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bool "PowerPC architecture"
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select HAVE_PRIVATE_LIBGCC
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select SUPPORT_OF_CONTROL
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select SYS_BOOT_GET_CMDLINE
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select SYS_BOOT_GET_KBD
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config RISCV
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bool "RISC-V architecture"
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select CREATE_ARCH_SYMLINK
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select SUPPORT_OF_CONTROL
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select OF_CONTROL
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select DM
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select SPL_SEPARATE_BSS if SPL
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imply DM_SERIAL
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imply DM_ETH
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imply DM_EVENT
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imply DM_MMC
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imply DM_SPI
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imply DM_SPI_FLASH
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imply BLK
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imply CLK
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imply MTD
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imply TIMER
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imply CMD_DM
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imply SPL_DM
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imply SPL_OF_CONTROL
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imply SPL_LIBCOMMON_SUPPORT
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imply SPL_LIBGENERIC_SUPPORT
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imply SPL_SERIAL
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imply SPL_TIMER
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config SANDBOX
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bool "Sandbox"
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select ARCH_SUPPORTS_LTO
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select BOARD_LATE_INIT
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select BZIP2
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select CMD_POWEROFF
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select DM
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select DM_FUZZING_ENGINE
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select DM_GPIO
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select DM_I2C
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select DM_KEYBOARD
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select DM_MMC
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select DM_SERIAL
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select DM_SPI
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select DM_SPI_FLASH
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select GZIP_COMPRESSED
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select HAVE_BLOCK_DEVICE
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select LZO
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select OF_BOARD_SETUP
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select PCI_ENDPOINT
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select SPI
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select SUPPORT_OF_CONTROL
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select SYSRESET_CMD_POWEROFF
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select SYS_CACHE_SHIFT_4
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select IRQ
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select SUPPORT_EXTENSION_SCAN
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select SUPPORT_ACPI
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imply BITREVERSE
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select BLOBLIST
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imply LTO
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imply CMD_DM
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imply CMD_EXCEPTION
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imply CMD_GETTIME
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imply CMD_HASH
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imply CMD_IO
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imply CMD_IOTRACE
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imply CMD_LZMADEC
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imply CMD_SATA
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imply CMD_SF
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imply CMD_SF_TEST
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imply CRC32_VERIFY
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imply FAT_WRITE
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imply FIRMWARE
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imply FUZZING_ENGINE_SANDBOX
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imply HASH_VERIFY
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imply LZMA
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imply TEE
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imply AVB_VERIFY
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imply LIBAVB
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imply CMD_AVB
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imply PARTITION_TYPE_GUID
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imply SCP03
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imply CMD_SCP03
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imply UDP_FUNCTION_FASTBOOT
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imply VIRTIO_MMIO
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imply VIRTIO_PCI
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imply VIRTIO_SANDBOX
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imply VIRTIO_BLK
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imply VIRTIO_NET
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imply DM_SOUND
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imply PCI_SANDBOX_EP
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imply PCH
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imply PHYLIB
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imply DM_MDIO
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imply DM_MDIO_MUX
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imply ACPI_PMC
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imply ACPI_PMC_SANDBOX
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imply CMD_PMC
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imply CMD_CLONE
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imply SILENT_CONSOLE
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imply BOOTARGS_SUBST
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imply PHY_FIXED
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imply DM_DSA
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imply CMD_EXTENSION
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imply KEYBOARD
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imply PHYSMEM
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imply GENERATE_ACPI_TABLE
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imply BINMAN
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config SH
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bool "SuperH architecture"
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select HAVE_PRIVATE_LIBGCC
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select SUPPORT_OF_CONTROL
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config X86
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bool "x86 architecture"
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select SUPPORT_SPL
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select SUPPORT_TPL
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select CREATE_ARCH_SYMLINK
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select DM
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select HAVE_ARCH_IOMAP
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select HAVE_PRIVATE_LIBGCC
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select OF_CONTROL
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select PCI
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select SUPPORT_ACPI
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select SUPPORT_OF_CONTROL
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select SYS_CACHE_SHIFT_6
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select TIMER
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select USE_PRIVATE_LIBGCC
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select X86_TSC_TIMER
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select IRQ
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imply HAS_ROM if X86_RESET_VECTOR
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imply BLK
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imply CMD_DM
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imply CMD_FPGA_LOADMK
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imply CMD_GETTIME
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imply CMD_IO
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imply CMD_IRQ
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imply CMD_PCI
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imply CMD_SF
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imply CMD_SF_TEST
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imply CMD_ZBOOT
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imply DM_ETH
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imply DM_EVENT
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imply DM_GPIO
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imply DM_KEYBOARD
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imply DM_MMC
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imply DM_RTC
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imply DM_SCSI
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imply DM_SERIAL
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imply DM_SPI
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imply DM_SPI_FLASH
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imply DM_USB
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imply DM_VIDEO
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imply SYSRESET
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imply SPL_SYSRESET
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imply SYSRESET_X86
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imply USB_ETHER_ASIX
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imply USB_ETHER_SMSC95XX
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imply USB_HOST_ETHER
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imply PCH
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imply PHYSMEM
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imply RTC_MC146818
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imply ACPIGEN if !QEMU && !EFI_APP
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imply SYSINFO if GENERATE_SMBIOS_TABLE
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imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
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imply TIMESTAMP
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# Thing to enable for when SPL/TPL are enabled: SPL
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imply SPL_DM
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imply SPL_OF_LIBFDT
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imply SPL_DRIVERS_MISC
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imply SPL_GPIO
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imply SPL_PINCTRL
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imply SPL_LIBCOMMON_SUPPORT
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imply SPL_LIBGENERIC_SUPPORT
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imply SPL_SERIAL
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imply SPL_SPI_FLASH_SUPPORT
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imply SPL_SPI
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imply SPL_OF_CONTROL
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imply SPL_TIMER
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imply SPL_REGMAP
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imply SPL_SYSCON
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# TPL
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imply TPL_DM
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imply TPL_DRIVERS_MISC
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imply TPL_GPIO
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imply TPL_PINCTRL
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imply TPL_LIBCOMMON_SUPPORT
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imply TPL_LIBGENERIC_SUPPORT
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imply TPL_SERIAL
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imply TPL_OF_CONTROL
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imply TPL_TIMER
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imply TPL_REGMAP
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imply TPL_SYSCON
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config XTENSA
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bool "Xtensa architecture"
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select CREATE_ARCH_SYMLINK
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select SUPPORT_OF_CONTROL
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endchoice
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config SYS_ARCH
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string
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help
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This option should contain the architecture name to build the
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appropriate arch/<CONFIG_SYS_ARCH> directory.
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All the architectures should specify this option correctly.
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config SYS_CPU
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string
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help
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This option should contain the CPU name to build the correct
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arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
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This is optional. For those targets without the CPU directory,
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leave this option empty.
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config SYS_SOC
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string
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help
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This option should contain the SoC name to build the directory
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arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
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This is optional. For those targets without the SoC directory,
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leave this option empty.
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config SYS_VENDOR
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string
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help
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This option should contain the vendor name of the target board.
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If it is set and
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board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
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directory is compiled.
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If CONFIG_SYS_BOARD is also set, the sources under
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board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
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This is optional. For those targets without the vendor directory,
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leave this option empty.
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config SYS_BOARD
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string
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help
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This option should contain the name of the target board.
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If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
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or board/<CONFIG_SYS_BOARD> directory is compiled depending on
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whether CONFIG_SYS_VENDOR is set or not.
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This is optional. For those targets without the board directory,
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leave this option empty.
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config SYS_CONFIG_NAME
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string
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help
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This option should contain the base name of board header file.
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The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
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should be included from include/config.h.
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config SYS_DISABLE_DCACHE_OPS
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bool
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help
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This option disables dcache flush and dcache invalidation
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operations. For example, on coherent systems where cache
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operatios are not required, enable this option to avoid them.
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Note that, its up to the individual architectures to implement
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this functionality.
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config SYS_IMMR
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hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
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depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
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default 0xFF000000 if MPC8xx
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default 0xF0000000 if ARCH_MPC8313
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default 0xE0000000 if MPC83xx && !ARCH_MPC8313
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default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
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default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
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ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
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ARCH_P2020
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default SYS_CCSRBAR_DEFAULT
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help
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Address for the Internal Memory-Mapped Registers (IMMR) window used
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to configure the features of many Freescale / NXP SoCs.
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config SKIP_LOWLEVEL_INIT
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bool "Skip the calls to certain low level initialization functions"
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depends on ARM || MIPS || RISCV
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help
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If enabled, then certain low level initializations (like setting up
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the memory controller) are omitted and/or U-Boot does not relocate
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itself into RAM.
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Normally this variable MUST NOT be defined. The only exception is
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when U-Boot is loaded (to RAM) by some other boot loader or by a
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debugger which performs these initializations itself.
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config SPL_SKIP_LOWLEVEL_INIT
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bool "Skip the calls to certain low level initialization functions"
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depends on SPL && (ARM || MIPS || RISCV)
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help
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If enabled, then certain low level initializations (like setting up
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the memory controller) are omitted and/or U-Boot does not relocate
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itself into RAM.
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Normally this variable MUST NOT be defined. The only exception is
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when U-Boot is loaded (to RAM) by some other boot loader or by a
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debugger which performs these initializations itself.
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config TPL_SKIP_LOWLEVEL_INIT
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bool "Skip the calls to certain low level initialization functions"
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depends on SPL && ARM
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help
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If enabled, then certain low level initializations (like setting up
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the memory controller) are omitted and/or U-Boot does not relocate
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itself into RAM.
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Normally this variable MUST NOT be defined. The only exception is
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when U-Boot is loaded (to RAM) by some other boot loader or by a
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debugger which performs these initializations itself.
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config SKIP_LOWLEVEL_INIT_ONLY
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bool "Skip the call to lowlevel_init during early boot ONLY"
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depends on ARM
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help
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This allows just the call to lowlevel_init() to be skipped. The
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normal CP15 init (such as enabling the instruction cache) is still
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performed.
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config SPL_SKIP_LOWLEVEL_INIT_ONLY
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bool "Skip the call to lowlevel_init during early boot ONLY"
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depends on SPL && ARM
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help
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This allows just the call to lowlevel_init() to be skipped. The
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normal CP15 init (such as enabling the instruction cache) is still
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performed.
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config TPL_SKIP_LOWLEVEL_INIT_ONLY
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bool "Skip the call to lowlevel_init during early boot ONLY"
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depends on TPL && ARM
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help
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This allows just the call to lowlevel_init() to be skipped. The
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normal CP15 init (such as enabling the instruction cache) is still
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performed.
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source "arch/arc/Kconfig"
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source "arch/arm/Kconfig"
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source "arch/m68k/Kconfig"
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source "arch/microblaze/Kconfig"
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source "arch/mips/Kconfig"
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source "arch/nios2/Kconfig"
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source "arch/powerpc/Kconfig"
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source "arch/sandbox/Kconfig"
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source "arch/sh/Kconfig"
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source "arch/x86/Kconfig"
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source "arch/xtensa/Kconfig"
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source "arch/riscv/Kconfig"
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source "board/freescale/common/Kconfig"
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source "board/keymile/Kconfig"
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if MIPS || MICROBLAZE
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choice
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prompt "Endianness selection"
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help
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Some MIPS boards can be configured for either little or big endian
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byte order. These modes require different U-Boot images. In general there
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is one preferred byteorder for a particular system but some systems are
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just as commonly used in the one or the other endianness.
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config SYS_BIG_ENDIAN
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bool "Big endian"
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depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
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config SYS_LITTLE_ENDIAN
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bool "Little endian"
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depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE
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endchoice
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endif
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