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30f47c0f1b
Add power and reset headers to be sources by Versal dtses. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
124 lines
2.8 KiB
C
124 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 Xilinx Inc.
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*
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*/
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#ifndef _DT_BINDINGS_CLK_VERSAL_H
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#define _DT_BINDINGS_CLK_VERSAL_H
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#define PMC_PLL 1
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#define APU_PLL 2
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#define RPU_PLL 3
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#define CPM_PLL 4
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#define NOC_PLL 5
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#define PLL_MAX 6
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#define PMC_PRESRC 7
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#define PMC_POSTCLK 8
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#define PMC_PLL_OUT 9
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#define PPLL 10
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#define NOC_PRESRC 11
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#define NOC_POSTCLK 12
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#define NOC_PLL_OUT 13
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#define NPLL 14
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#define APU_PRESRC 15
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#define APU_POSTCLK 16
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#define APU_PLL_OUT 17
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#define APLL 18
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#define RPU_PRESRC 19
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#define RPU_POSTCLK 20
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#define RPU_PLL_OUT 21
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#define RPLL 22
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#define CPM_PRESRC 23
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#define CPM_POSTCLK 24
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#define CPM_PLL_OUT 25
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#define CPLL 26
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#define PPLL_TO_XPD 27
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#define NPLL_TO_XPD 28
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#define APLL_TO_XPD 29
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#define RPLL_TO_XPD 30
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#define EFUSE_REF 31
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#define SYSMON_REF 32
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#define IRO_SUSPEND_REF 33
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#define USB_SUSPEND 34
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#define SWITCH_TIMEOUT 35
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#define RCLK_PMC 36
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#define RCLK_LPD 37
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#define WDT 38
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#define TTC0 39
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#define TTC1 40
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#define TTC2 41
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#define TTC3 42
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#define GEM_TSU 43
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#define GEM_TSU_LB 44
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#define MUXED_IRO_DIV2 45
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#define MUXED_IRO_DIV4 46
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#define PSM_REF 47
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#define GEM0_RX 48
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#define GEM0_TX 49
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#define GEM1_RX 50
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#define GEM1_TX 51
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#define CPM_CORE_REF 52
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#define CPM_LSBUS_REF 53
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#define CPM_DBG_REF 54
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#define CPM_AUX0_REF 55
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#define CPM_AUX1_REF 56
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#define QSPI_REF 57
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#define OSPI_REF 58
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#define SDIO0_REF 59
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#define SDIO1_REF 60
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#define PMC_LSBUS_REF 61
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#define I2C_REF 62
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#define TEST_PATTERN_REF 63
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#define DFT_OSC_REF 64
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#define PMC_PL0_REF 65
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#define PMC_PL1_REF 66
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#define PMC_PL2_REF 67
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#define PMC_PL3_REF 68
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#define CFU_REF 69
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#define SPARE_REF 70
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#define NPI_REF 71
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#define HSM0_REF 72
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#define HSM1_REF 73
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#define SD_DLL_REF 74
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#define FPD_TOP_SWITCH 75
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#define FPD_LSBUS 76
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#define ACPU 77
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#define DBG_TRACE 78
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#define DBG_FPD 79
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#define LPD_TOP_SWITCH 80
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#define ADMA 81
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#define LPD_LSBUS 82
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#define CPU_R5 83
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#define CPU_R5_CORE 84
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#define CPU_R5_OCM 85
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#define CPU_R5_OCM2 86
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#define IOU_SWITCH 87
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#define GEM0_REF 88
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#define GEM1_REF 89
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#define GEM_TSU_REF 90
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#define USB0_BUS_REF 91
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#define UART0_REF 92
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#define UART1_REF 93
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#define SPI0_REF 94
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#define SPI1_REF 95
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#define CAN0_REF 96
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#define CAN1_REF 97
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#define I2C0_REF 98
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#define I2C1_REF 99
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#define DBG_LPD 100
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#define TIMESTAMP_REF 101
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#define DBG_TSTMP 102
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#define CPM_TOPSW_REF 103
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#define USB3_DUAL_REF 104
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#define OUTCLK_MAX 105
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#define REF_CLK 106
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#define PL_ALT_REF_CLK 107
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#define MUXED_IRO 108
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#define PL_EXT 109
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#define PL_LB 110
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#define MIO_50_OR_51 111
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#define MIO_24_OR_25 112
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#endif
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