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https://github.com/u-boot/u-boot.git
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4e5909450e
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NAND namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
104 lines
2.8 KiB
C
104 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2019-2020 NXP
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*/
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#ifndef __LS1046AFRWY_H__
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#define __LS1046AFRWY_H__
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#include "ls1046a_common.h"
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#define CONFIG_SYS_UBOOT_BASE 0x40100000
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/*
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* NAND Flash Definitions
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*/
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#define CFG_SYS_NAND_BASE 0x7e800000
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#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
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#define CFG_SYS_NAND_CSPR_EXT (0x0)
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#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_NAND \
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| CSPR_V)
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#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
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#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
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| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
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| CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
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| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
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#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
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FTIM0_NAND_TWP(0x18) | \
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FTIM0_NAND_TWCHT(0x7) | \
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FTIM0_NAND_TWH(0xa))
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#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
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FTIM1_NAND_TWBE(0x39) | \
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FTIM1_NAND_TRR(0xe) | \
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FTIM1_NAND_TRP(0x18))
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#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
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FTIM2_NAND_TREH(0xa) | \
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FTIM2_NAND_TWHRE(0x1e))
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#define CFG_SYS_NAND_FTIM3 0x0
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#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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/* IFC Timing Params */
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#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
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/* EEPROM */
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#define I2C_RETIMER_ADDR 0x18
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/* I2C bus multiplexer */
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#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
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#define I2C_MUX_CH_DEFAULT 0x1 /* Channel 0*/
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#define I2C_MUX_CH_RTC 0x1 /* Channel 0*/
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/* RTC */
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#define RTC
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/
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#define CONFIG_SYS_RTC_BUS_NUM 0
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/*
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* Environment
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*/
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#define CFG_SYS_FSL_QSPI_BASE 0x40000000
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#undef BOOT_TARGET_DEVICES
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(USB, usb, 0) \
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func(DHCP, dhcp, na)
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/* FMan */
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#ifdef CONFIG_SYS_DPAA_FMAN
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#define QSGMII_PORT1_PHY_ADDR 0x1c
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#define QSGMII_PORT2_PHY_ADDR 0x1d
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#define QSGMII_PORT3_PHY_ADDR 0x1e
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#define QSGMII_PORT4_PHY_ADDR 0x1f
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#define FDT_SEQ_MACADDR_FROM_ENV
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#endif
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#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
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"env exists secureboot && esbc_halt;;"
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#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
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"env exists secureboot && esbc_halt;"
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#include <asm/fsl_secure_boot.h>
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#endif /* __LS1046AFRWY_H__ */
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