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https://github.com/u-boot/u-boot.git
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d9abba8254
This patch adds generic support for the Samsung s3c2440 processor. Global s3c24x0 changes to struct members converting from upper case to lower case. Signed-off-by: Craig Nauman <cnauman@diagraph.com> Cc: kevin.morfitt@fearnside-systems.co.uk Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
194 lines
4.4 KiB
C
194 lines
4.4 KiB
C
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* (C) Copyright 2005
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* JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/arch/s3c24x0_cpu.h>
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#if defined(CONFIG_CMD_NAND)
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#include <linux/mtd/nand.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#define FCLK_SPEED 1
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#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
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#define M_MDIV 0xC3
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#define M_PDIV 0x4
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#define M_SDIV 0x1
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#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
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#define M_MDIV 0x5c
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#define M_PDIV 0x4
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#define M_SDIV 0x0
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#endif
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#define USB_CLOCK 1
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#if USB_CLOCK==0
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#define U_M_MDIV 0xA1
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#define U_M_PDIV 0x3
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#define U_M_SDIV 0x1
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#elif USB_CLOCK==1
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#define U_M_MDIV 0x48
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#define U_M_PDIV 0x3
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#define U_M_SDIV 0x2
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#endif
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static inline void delay (unsigned long loops)
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{
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0" (loops));
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}
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init (void)
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{
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struct s3c24x0_clock_power * const clk_power =
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s3c24x0_get_base_clock_power();
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struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
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/* to reduce PLL lock time, adjust the LOCKTIME register */
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clk_power->locktime = 0xFFFFFF;
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/* configure MPLL */
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clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
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/* some delay between MPLL and UPLL */
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delay (4000);
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/* configure UPLL */
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clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
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/* some delay between MPLL and UPLL */
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delay (8000);
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/* set up the I/O ports */
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gpio->gpacon = 0x007FFFFF;
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gpio->gpbcon = 0x00044556;
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gpio->gpbup = 0x000007FF;
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gpio->gpccon = 0xAAAAAAAA;
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gpio->gpcup = 0x0000FFFF;
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gpio->gpdcon = 0xAAAAAAAA;
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gpio->gpdup = 0x0000FFFF;
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gpio->gpecon = 0xAAAAAAAA;
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gpio->gpeup = 0x0000FFFF;
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gpio->gpfcon = 0x000055AA;
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gpio->gpfup = 0x000000FF;
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gpio->gpgcon = 0xFF95FF3A;
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gpio->gpgup = 0x0000FFFF;
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gpio->gphcon = 0x0016FAAA;
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gpio->gphup = 0x000007FF;
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gpio->extint0 = 0x22222222;
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gpio->extint1 = 0x22222222;
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gpio->extint2 = 0x22222222;
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/* arch number of SMDK2410-Board */
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gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0x30000100;
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icache_enable();
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dcache_enable();
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return 0;
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}
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int dram_init (void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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#if defined(CONFIG_CMD_NAND)
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extern ulong nand_probe(ulong physadr);
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static inline void NF_Reset(void)
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{
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int i;
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NF_SetCE(NFCE_LOW);
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NF_Cmd(0xFF); /* reset command */
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for(i = 0; i < 10; i++); /* tWB = 100ns. */
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NF_WaitRB(); /* wait 200~500us; */
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NF_SetCE(NFCE_HIGH);
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}
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static inline void NF_Init(void)
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{
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#if 1
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#define TACLS 0
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#define TWRPH0 3
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#define TWRPH1 0
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#else
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#define TACLS 0
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#define TWRPH0 4
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#define TWRPH1 2
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#endif
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NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
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/*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
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/* 1 1 1 1, 1 xxx, r xxx, r xxx */
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/* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */
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NF_Reset();
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}
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void nand_init(void)
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{
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struct s3c2410_nand * const nand = s3c2410_get_base_nand();
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NF_Init();
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#ifdef DEBUG
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printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
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#endif
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printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
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}
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#endif
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_CS8900
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rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
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#endif
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return rc;
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}
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#endif
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