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Often on boards exists a circuit which switches power on/off to LCD display. Due to the need of limiting the in-rush current the output voltage from this circuit rises "slowly", so it is necessary to wait a bit (VCC ramp up time) before starting output on LCD-pins. This time is specified in <n> ms within the panel-settings, called "pup_delay" Further some LCDs need a couple of frames to stabilize the image on it. We have now the possibility to wait some time after starting output on LCD. This time is also specified in <n> ms within panel-settings, called "pon_delay" Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
73 lines
2.2 KiB
C
73 lines
2.2 KiB
C
/*
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* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> -
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* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef AM335X_FB_H
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#define AM335X_FB_H
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#define HSVS_CONTROL (0x01 << 25) /*
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* 0 = lcd_lp and lcd_fp are driven on
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* opposite edges of pixel clock than
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* the lcd_pixel_o
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* 1 = lcd_lp and lcd_fp are driven
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* according to bit 24 Note that this
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* bit MUST be set to '0' for Passive
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* Matrix displays the edge timing is
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* fixed
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*/
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#define HSVS_RISEFALL (0x01 << 24) /*
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* 0 = lcd_lp and lcd_fp are driven on
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* the rising edge of pixel clock (bit
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* 25 must be set to 1)
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* 1 = lcd_lp and lcd_fp are driven on
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* the falling edge of pixel clock (bit
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* 25 must be set to 1)
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*/
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#define DE_INVERT (0x01 << 23) /*
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* 0 = DE is low-active
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* 1 = DE is high-active
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*/
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#define PXCLK_INVERT (0x01 << 22) /*
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* 0 = pix-clk is high-active
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* 1 = pic-clk is low-active
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*/
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#define HSYNC_INVERT (0x01 << 21) /*
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* 0 = HSYNC is active high
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* 1 = HSYNC is avtive low
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*/
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#define VSYNC_INVERT (0x01 << 20) /*
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* 0 = VSYNC is active high
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* 1 = VSYNC is active low
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*/
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struct am335x_lcdpanel {
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unsigned int hactive; /* Horizontal active area */
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unsigned int vactive; /* Vertical active area */
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unsigned int bpp; /* bits per pixel */
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unsigned int hfp; /* Horizontal front porch */
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unsigned int hbp; /* Horizontal back porch */
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unsigned int hsw; /* Horizontal Sync Pulse Width */
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unsigned int vfp; /* Vertical front porch */
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unsigned int vbp; /* Vertical back porch */
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unsigned int vsw; /* Vertical Sync Pulse Width */
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unsigned int pxl_clk_div; /* Pixel clock divider*/
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unsigned int pol; /* polarity of sync, clock signals */
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unsigned int pup_delay; /*
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* time in ms after power on to
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* initialization of lcd-controller
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* (VCC ramp up time)
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*/
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unsigned int pon_delay; /*
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* time in ms after initialization of
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* lcd-controller (pic stabilization)
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*/
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void (*panel_power_ctrl)(int); /* fp for power on/off display */
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};
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int am335xfb_init(struct am335x_lcdpanel *panel);
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#endif /* AM335X_FB_H */
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