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5d88902401
The EFI subsystem accesses the real time clock and is enabled by default. So we should drop any CONFIG_CMD_DATE dependency from the real time clock drivers. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
167 lines
4.3 KiB
C
167 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2006
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* Markus Klotzbuecher, mk@denx.de
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*/
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/*
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* Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
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* Extremly Accurate DS3231 Real Time Clock (RTC).
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*
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* copied from ds1337.c
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*/
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#include <common.h>
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#include <command.h>
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#include <rtc.h>
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#include <i2c.h>
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/*
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* RTC register addresses
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*/
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#define RTC_SEC_REG_ADDR 0x0
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#define RTC_MIN_REG_ADDR 0x1
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#define RTC_HR_REG_ADDR 0x2
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#define RTC_DAY_REG_ADDR 0x3
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#define RTC_DATE_REG_ADDR 0x4
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#define RTC_MON_REG_ADDR 0x5
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#define RTC_YR_REG_ADDR 0x6
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#define RTC_CTL_REG_ADDR 0x0e
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#define RTC_STAT_REG_ADDR 0x0f
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/*
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* RTC control register bits
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*/
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#define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */
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#define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */
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#define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */
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#define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */
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#define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */
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#define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */
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/*
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* RTC status register bits
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*/
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#define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */
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#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
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#define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */
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#define RTC_STAT_BIT_BB32KHZ 0x40 /* Battery backed 32KHz Output */
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#define RTC_STAT_BIT_EN32KHZ 0x8 /* Enable 32KHz Output */
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static uchar rtc_read (uchar reg);
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static void rtc_write (uchar reg, uchar val);
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/*
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* Get the current time from the RTC
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*/
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int rtc_get (struct rtc_time *tmp)
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{
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int rel = 0;
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uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
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control = rtc_read (RTC_CTL_REG_ADDR);
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status = rtc_read (RTC_STAT_REG_ADDR);
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sec = rtc_read (RTC_SEC_REG_ADDR);
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min = rtc_read (RTC_MIN_REG_ADDR);
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hour = rtc_read (RTC_HR_REG_ADDR);
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wday = rtc_read (RTC_DAY_REG_ADDR);
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mday = rtc_read (RTC_DATE_REG_ADDR);
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mon_cent = rtc_read (RTC_MON_REG_ADDR);
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year = rtc_read (RTC_YR_REG_ADDR);
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debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
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"hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
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year, mon_cent, mday, wday, hour, min, sec, control, status);
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if (status & RTC_STAT_BIT_OSF) {
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printf ("### Warning: RTC oscillator has stopped\n");
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/* clear the OSF flag */
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rtc_write (RTC_STAT_REG_ADDR,
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rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
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rel = -1;
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}
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tmp->tm_sec = bcd2bin (sec & 0x7F);
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tmp->tm_min = bcd2bin (min & 0x7F);
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tmp->tm_hour = bcd2bin (hour & 0x3F);
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tmp->tm_mday = bcd2bin (mday & 0x3F);
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tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
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tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
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tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
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tmp->tm_yday = 0;
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tmp->tm_isdst= 0;
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debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
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tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
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tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
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return rel;
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}
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/*
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* Set the RTC
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*/
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int rtc_set (struct rtc_time *tmp)
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{
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uchar century;
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debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
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tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
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tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
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rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
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century = (tmp->tm_year >= 2000) ? 0x80 : 0;
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rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);
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rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
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rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
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rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
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rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
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rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
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return 0;
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}
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/*
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* Reset the RTC. We also enable the oscillator output on the
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* SQW/INTB* pin and program it for 32,768 Hz output. Note that
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* according to the datasheet, turning on the square wave output
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* increases the current drain on the backup battery from about
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* 600 nA to 2uA.
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*/
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void rtc_reset (void)
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{
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rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2);
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}
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/*
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* Enable 32KHz output
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*/
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void rtc_enable_32khz_output(void)
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{
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rtc_write(RTC_STAT_REG_ADDR,
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RTC_STAT_BIT_BB32KHZ | RTC_STAT_BIT_EN32KHZ);
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}
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/*
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* Helper functions
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*/
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static
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uchar rtc_read (uchar reg)
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{
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return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
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}
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static void rtc_write (uchar reg, uchar val)
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{
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i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
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}
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