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b6e4c4033c
- add support for the PATI board (MPC555) - add SPI support for the MPC5xx * Patch by Anders Larsen, 08 Dec 2003: add configuration options CONFIG_SERIAL_TAG and CONFIG_REVISION_TAG to pass ATAG_SERIAL and ATAG_REVISION, resp., to the ARM target; cleanup some redundand #defines
124 lines
3.3 KiB
C
124 lines
3.3 KiB
C
/*
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* (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation,
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*/
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/*
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* File: cpu_init.c
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*
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* Discription: Contains initialisation functions to setup
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* the cpu properly
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*
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*/
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#include <common.h>
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#include <mpc5xx.h>
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#include <watchdog.h>
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/*
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* Setup essential cpu registers to run
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*/
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void cpu_init_f (volatile immap_t * immr)
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{
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volatile memctl5xx_t *memctl = &immr->im_memctl;
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ulong reg;
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/* SYPCR - contains watchdog control. This will enable watchdog */
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/* if CONFIG_WATCHDOG is set */
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immr->im_siu_conf.sc_sypcr = CFG_SYPCR;
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#if defined(CONFIG_WATCHDOG)
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reset_5xx_watchdog (immr);
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#endif
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/* SIUMCR - contains debug pin configuration */
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immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR;
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/* Initialize timebase. Unlock TBSCRK */
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immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
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immr->im_sit.sit_tbscr = CFG_TBSCR;
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/* Full IMB bus speed */
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immr->im_uimb.uimb_umcr = CFG_UMCR;
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/* Time base and decrementer will be enables (TBE) */
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/* in init_timebase() in time.c called from board_init_f(). */
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/* Initialize the PIT. Unlock PISCRK */
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immr->im_sitk.sitk_piscrk = KAPWR_KEY;
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immr->im_sit.sit_piscr = CFG_PISCR;
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#if !defined(CONFIG_PATI)
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/* PATI sest PLL in start.S */
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/* PLL (CPU clock) settings */
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immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
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/* If CFG_PLPRCR (set in the various *_config.h files) tries to
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* set the MF field, then just copy CFG_PLPRCR over car_plprcr,
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* otherwise OR in CFG_PLPRCR so we do not change the currentMF
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* field value.
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*/
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#if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0)
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reg = CFG_PLPRCR; /* reset control bits */
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#else
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reg = immr->im_clkrst.car_plprcr;
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reg &= PLPRCR_MF_MSK; /* isolate MF field */
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reg |= CFG_PLPRCR; /* reset control bits */
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#endif
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immr->im_clkrst.car_plprcr = reg;
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#endif /* !defined(CONFIG_PATI) */
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/* System integration timers. CFG_MASK has EBDF configuration */
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immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
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reg = immr->im_clkrst.car_sccr;
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reg &= SCCR_MASK;
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reg |= CFG_SCCR;
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immr->im_clkrst.car_sccr = reg;
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/* Memory Controller */
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memctl->memc_br0 = CFG_BR0_PRELIM;
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memctl->memc_or0 = CFG_OR0_PRELIM;
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#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
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memctl->memc_or1 = CFG_OR1_PRELIM;
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memctl->memc_br1 = CFG_BR1_PRELIM;
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#endif
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#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
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memctl->memc_or2 = CFG_OR2_PRELIM;
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memctl->memc_br2 = CFG_BR2_PRELIM;
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#endif
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#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
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memctl->memc_or3 = CFG_OR3_PRELIM;
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memctl->memc_br3 = CFG_BR3_PRELIM;
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#endif
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}
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/*
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* Initialize higher level parts of cpu
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*/
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int cpu_init_r (void)
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{
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/* Nothing to do at the moment */
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return (0);
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}
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