mirror of
https://github.com/u-boot/u-boot.git
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67c145a836
Use DM for both MMC and USB subsystems and use dedicated DTS for U-Boot configuration. Disable SPL support for GPIO and remove EVMSK leftover for DDR power control via GPIO. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
119 lines
4.4 KiB
C
119 lines
4.4 KiB
C
/*
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* mux.c
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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#include <i2c.h>
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#include "board.h"
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static struct module_pin_mux uart0_pin_mux[] = {
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{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
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{-1},
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};
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static struct module_pin_mux mmc0_pin_mux[] = {
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{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
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{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
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{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
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{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
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{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
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{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
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{-1},
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};
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static struct module_pin_mux i2c1_pin_mux[] = {
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{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
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PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
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{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
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PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
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{-1},
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};
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static struct module_pin_mux rmii1_pin_mux[] = {
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{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
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{OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */
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{OFFSET(mii1_txd1), MODE(1)}, /* RGMII1_TCTL */
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{OFFSET(mii1_txd0), MODE(1)}, /* RGMII1_TCTL */
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{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
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{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
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{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RGMII1_TCTL */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{-1},
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};
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static struct module_pin_mux rgmii2_pin_mux[] = {
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{OFFSET(gpmc_a0), MODE(2)}, /* RGMII1_TCTL */
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{OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
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{OFFSET(gpmc_a2), MODE(2)}, /* RGMII1_TD3 */
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{OFFSET(gpmc_a3), MODE(2)}, /* RGMII1_TD2 */
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{OFFSET(gpmc_a4), MODE(2)}, /* RGMII1_TD1 */
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{OFFSET(gpmc_a5), MODE(2)}, /* RGMII1_TD0 */
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{OFFSET(gpmc_a6), MODE(2)}, /* RGMII1_TCLK */
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{OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
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{OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
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{OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
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{OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
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{OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{-1},
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};
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static struct module_pin_mux nand_pin_mux[] = {
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{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
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{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
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{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
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{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
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{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
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{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
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{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
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{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
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{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
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{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
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{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
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{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
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{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
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{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
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{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
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{-1},
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};
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void enable_uart0_pin_mux(void)
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{
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configure_module_pin_mux(uart0_pin_mux);
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}
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void enable_i2c1_pin_mux(void)
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{
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configure_module_pin_mux(i2c1_pin_mux);
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}
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void enable_board_pin_mux()
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{
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configure_module_pin_mux(i2c1_pin_mux);
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configure_module_pin_mux(rgmii2_pin_mux);
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configure_module_pin_mux(rmii1_pin_mux);
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configure_module_pin_mux(mmc0_pin_mux);
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#if defined(CONFIG_NAND)
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configure_module_pin_mux(nand_pin_mux);
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#endif
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}
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