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855a496fe9
- Fix Gigabit Ethernet support for 440GX - Add Gigabit Ethernet Support to MII PHY utilities * Patch by Brad Kemp, 12 Mar 2004: Fixes for drivers/cfi_flash.c: - Better support for x8/x16 implementations - Added failure for AMD chips attempting to use CFG_FLASH_USE_BUFFER_WRITE - Added defines for AMD command and address constants * Patch by Leon Kukovec, 12 Mar 2004: Fix get_dentfromdir() to correctly handle deleted dentries * Patch by George G. Davis, 11 Mar 2004: Remove hard coded network settings in TI OMAP1610 H2 default board config * Patch by George G. Davis, 11 Mar 2004: add support for ADS GraphicsClient+ board.
130 lines
3.9 KiB
C
130 lines
3.9 KiB
C
/*----------------------------------------------------------------------------+
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| This source code has been made available to you by IBM on an AS-IS
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| basis. Anyone receiving this source is licensed under IBM
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| copyrights to use it in any way he or she deems fit, including
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| copying it, modifying it, compiling it, and redistributing it either
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| with or without modifications. No license under IBM patents or
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| patent applications is to be implied by the copyright license.
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| Any user of this software should understand that IBM cannot provide
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| technical support for this software and will not be responsible for
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| any consequences resulting from the use of this software.
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| Any person who transfers this source code or any derivative work
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| must include the IBM copyright notice, this paragraph, and the
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| preceding two paragraphs in the transferred software.
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| COPYRIGHT I B M CORPORATION 1999
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| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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+----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------+
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| File Name: miiphy.h
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| Function: Include file defining PHY registers.
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| Author: Mark Wisner
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| Change Activity-
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| Date Description of Change BY
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| --------- --------------------- ---
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| 04-May-99 Created MKW
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| 07-Jul-99 Added full duplex support MKW
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| 08-Sep-01 Tweaks gvb
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+----------------------------------------------------------------------------*/
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#ifndef _miiphy_h_
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#define _miiphy_h_
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int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value);
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int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value);
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int miiphy_info(unsigned char addr, unsigned int *oui, unsigned char *model,
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unsigned char *rev);
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int miiphy_reset(unsigned char addr);
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int miiphy_speed(unsigned char addr);
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int miiphy_duplex(unsigned char addr);
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#ifdef CFG_FAULT_ECHO_LINK_DOWN
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int miiphy_link(unsigned char addr);
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#endif
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/* phy seed setup */
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#define AUTO 99
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#define _1000BASET 1000
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#define _100BASET 100
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#define _10BASET 10
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#define HALF 22
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#define FULL 44
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/* phy register offsets */
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#define PHY_BMCR 0x00
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#define PHY_BMSR 0x01
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#define PHY_PHYIDR1 0x02
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#define PHY_PHYIDR2 0x03
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#define PHY_ANAR 0x04
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#define PHY_ANLPAR 0x05
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#define PHY_ANER 0x06
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#define PHY_ANNPTR 0x07
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#define PHY_ANLPNP 0x08
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#define PHY_1000BTCR 0x09
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#define PHY_1000BTSR 0x0A
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#define PHY_PHYSTS 0x10
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#define PHY_MIPSCR 0x11
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#define PHY_MIPGSR 0x12
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#define PHY_DCR 0x13
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#define PHY_FCSCR 0x14
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#define PHY_RECR 0x15
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#define PHY_PCSR 0x16
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#define PHY_LBR 0x17
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#define PHY_10BTSCR 0x18
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#define PHY_PHYCTRL 0x19
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/* PHY BMCR */
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#define PHY_BMCR_RESET 0x8000
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#define PHY_BMCR_LOOP 0x4000
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#define PHY_BMCR_100MB 0x2000
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#define PHY_BMCR_AUTON 0x1000
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#define PHY_BMCR_POWD 0x0800
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#define PHY_BMCR_ISO 0x0400
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#define PHY_BMCR_RST_NEG 0x0200
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#define PHY_BMCR_DPLX 0x0100
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#define PHY_BMCR_COL_TST 0x0080
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/* phy BMSR */
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#define PHY_BMSR_100T4 0x8000
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#define PHY_BMSR_100TXF 0x4000
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#define PHY_BMSR_100TXH 0x2000
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#define PHY_BMSR_10TF 0x1000
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#define PHY_BMSR_10TH 0x0800
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#define PHY_BMSR_PRE_SUP 0x0040
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#define PHY_BMSR_AUTN_COMP 0x0020
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#define PHY_BMSR_RF 0x0010
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#define PHY_BMSR_AUTN_ABLE 0x0008
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#define PHY_BMSR_LS 0x0004
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#define PHY_BMSR_JD 0x0002
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#define PHY_BMSR_EXT 0x0001
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/*phy ANLPAR */
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#define PHY_ANLPAR_NP 0x8000
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#define PHY_ANLPAR_ACK 0x4000
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#define PHY_ANLPAR_RF 0x2000
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#define PHY_ANLPAR_T4 0x0200
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#define PHY_ANLPAR_TXFD 0x0100
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#define PHY_ANLPAR_TX 0x0080
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#define PHY_ANLPAR_10FD 0x0040
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#define PHY_ANLPAR_10 0x0020
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#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */
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/* PHY_1000BTSR */
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#define PHY_1000BTSR_MSCF 0x8000
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#define PHY_1000BTSR_MSCR 0x4000
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#define PHY_1000BTSR_LRS 0x2000
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#define PHY_1000BTSR_RRS 0x1000
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#define PHY_1000BTSR_1000FD 0x0800
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#define PHY_1000BTSR_1000HD 0x0400
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#endif
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