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https://github.com/u-boot/u-boot.git
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
320 lines
5.6 KiB
ArmAsm
320 lines
5.6 KiB
ArmAsm
/*
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* Copyright (C) 2009 Renesas Solutions Corp.
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* Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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*
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* board/espt/lowlevel_init.S
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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write32 WDTCSR_A, WDTCSR_D
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write32 WDTST_A, WDTST_D
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write32 WDTBST_A, WDTBST_D
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write32 CCR_A, CCR_CACHE_ICI_D
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write32 MMUCR_A, MMU_CONTROL_TI_D
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write32 MSTPCR0_A, MSTPCR0_D
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write32 MSTPCR1_A, MSTPCR1_D
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write32 RAMCR_A, RAMCR_D
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/*
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* Setting infomation from
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* original ESPT-GIGA bootloader register
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*/
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write32 MMSEL_A, MMSEL_D
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/* dummy */
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mov.l @r1, r2
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mov.l @r1, r2
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synco
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write32 BCR_A, BCR_D
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write32 CS0BCR_A, CS0BCR_D
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write32 CS0WCR_A, CS0WCR_D
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/*
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* DDR-SDRAM setting
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*/
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/* set DDR-SDRAM dummy read */
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write32 MMSEL_A, MMSEL_D
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write32 MMSEL_A, CS0_A
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/* set DDR-SDRAM bus/endian etc */
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write32 MIM_U_A, MIM_U_D
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write32 MIM_L_A, MIM_L_D0
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write32 SDR_L_A, SDR_L_A_D0
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write32 STR_L_A, STR_L_A_D0
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/* DDR-SDRAM access control */
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write32 MIM_L_A, MIM_L_D1
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write32 SCR_L_A, SCR_L_A_D0
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write32 SCR_L_A, SCR_L_A_D1
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write32 EMRS_A, EMRS_D
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write32 MRS1_A, MRS1_D
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write32 MIM_U_A, MIM_U_D
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write32 MIM_L_A, MIM_L_A_D2
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write32 SCR_L_A, SCR_L_A_D2
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write32 SCR_L_A, SCR_L_A_D2
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write32 MRS2_A, MRS2_D
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/* wait 200us */
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wait_timer REPEAT_R3
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/* GPIO setting */
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write16 PSEL0_A, PSEL0_D
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write16 PSEL1_A, PSEL1_D
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write16 PSEL2_A, PSEL2_D
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write16 PSEL3_A, PSEL3_D
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write16 PSEL4_A, PSEL4_D
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write8 PADR_A, PADR_D
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write16 PACR_A, PACR_D
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write8 PBDR_A, PBDR_D
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write16 PBCR_A, PBCR_D
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write8 PCDR_A, PCDR_D
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write16 PCCR_A, PCCR_D
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write8 PDDR_A, PDDR_D
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write16 PDCR_A, PDCR_D
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write16 PECR_A, PECR_D
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write16 PFCR_A, PFCR_D
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write16 PGCR_A, PGCR_D
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write16 PHCR_A, PHCR_D
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write16 PICR_A, PICR_D
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write8 PJDR_A, PJDR_D
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write16 PJCR_A, PJCR_D
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/* wait 50us */
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wait_timer REPEAT_R3
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write8 PKDR_A, PKDR_D
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write16 PKCR_A, PKCR_D
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write16 PLCR_A, PLCR_D
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write16 PMCR_A, PMCR_D
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write16 PNCR_A, PNCR_D
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write16 POCR_A, POCR_D
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/* ICR0 ,ICR1 */
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write32 ICR0_A, ICR0_D
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write32 ICR1_A, ICR1_D
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/* USB Host */
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write32 USB_USBHSC_A, USB_USBHSC_D
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write32 CCR_A, CCR_CACHE_D_2
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rts
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nop
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.align 2
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/* GPIO Crontrol Register */
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PACR_A: .long 0xFFEF0000
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PBCR_A: .long 0xFFEF0002
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PCCR_A: .long 0xFFEF0004
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PDCR_A: .long 0xFFEF0006
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PECR_A: .long 0xFFEF0008
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PFCR_A: .long 0xFFEF000A
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PGCR_A: .long 0xFFEF000C
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PHCR_A: .long 0xFFEF000E
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PICR_A: .long 0xFFEF0010
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PJCR_A: .long 0xFFEF0012
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PKCR_A: .long 0xFFEF0014
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PLCR_A: .long 0xFFEF0016
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PMCR_A: .long 0xFFEF0018
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PNCR_A: .long 0xFFEF001A
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POCR_A: .long 0xFFEF001C
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/* GPIO Data Register */
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PADR_A: .long 0xFFEF0020
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PBDR_A: .long 0xFFEF0022
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PCDR_A: .long 0xFFEF0024
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PDDR_A: .long 0xFFEF0026
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PJDR_A: .long 0xFFEF0032
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PKDR_A: .long 0xFFEF0034
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/* GPIO Set data */
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PADR_D: .long 0x00000000
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PACR_D: .word 0x1400
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.align 2
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PBDR_D: .long 0x00000000
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PBCR_D: .word 0x555A
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.align 2
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PCDR_D: .long 0x00000000
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PCCR_D: .word 0x5555
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.align 2
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PDDR_D: .long 0x00000000
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PDCR_D: .word 0x0155
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PECR_D: .word 0x0000
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PFCR_D: .word 0x0000
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PGCR_D: .word 0x0000
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PHCR_D: .word 0x0000
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PICR_D: .word 0x0800
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PJDR_D: .long 0x00000006
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PJCR_D: .word 0x5A57
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.align 2
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PKDR_D: .long 0x00000000
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PKCR_D: .word 0xFFF9
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.align 2
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PLCR_D: .word 0xC330
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PMCR_D: .word 0xFFFF
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PNCR_D: .word 0x0242
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POCR_D: .word 0x0000
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/* Pin Select */
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PSEL0_A: .long 0xFFEF0070
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PSEL1_A: .long 0xFFEF0072
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PSEL2_A: .long 0xFFEF0074
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PSEL3_A: .long 0xFFEF0076
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PSEL4_A: .long 0xFFEF0078
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PSEL0_D: .word 0x0001
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PSEL1_D: .word 0x2400
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PSEL2_D: .word 0x0000
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PSEL3_D: .word 0x2421
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PSEL4_D: .word 0x0000
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.align 2
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MMSEL_A: .long 0xFE600020
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BCR_A: .long 0xFF801000
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CS0BCR_A: .long 0xFF802000
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CS0WCR_A: .long 0xFF802008
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ICR0_A: .long 0xFFD00000
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ICR1_A: .long 0xFFD0001C
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MMSEL_D: .long 0xA5A50000
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BCR_D: .long 0x05000000
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CS0BCR_D: .long 0x232306F0
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CS0WCR_D: .long 0x00011104
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ICR0_D: .long 0x80C00000
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ICR1_D: .long 0x00020000
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/* RWBT Address */
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WDTST_A: .long 0xFFCC0000
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WDTCSR_A: .long 0xFFCC0004
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WDTBST_A: .long 0xFFCC0008
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/* RWBT Data */
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WDTST_D: .long 0x5A000FFF
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WDTCSR_D: .long 0xA5000000
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WDTBST_D: .long 0x55000000
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/* Cache Address */
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CCR_A: .long 0xFF00001C
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MMUCR_A: .long 0xFF000010
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RAMCR_A: .long 0xFF000074
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/* Cache Data */
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CCR_CACHE_ICI_D:.long 0x00000800
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CCR_CACHE_D_2: .long 0x00000103
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MMU_CONTROL_TI_D:.long 0x00000004
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RAMCR_D: .long 0x00000200
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/* Low power mode control Address */
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MSTPCR0_A: .long 0xFFC80030
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MSTPCR1_A: .long 0xFFC80038
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/* Low power mode control Data */
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MSTPCR0_D: .long 0x00000000
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MSTPCR1_D: .long 0x00000000
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REPEAT0_R3: .long 0x00002000
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REPEAT_R3: .long 0x00000200
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CS0_A: .long 0xA8000000
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MIM_U_A: .long 0xFE800008
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MIM_L_A: .long 0xFE80000C
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SCR_U_A: .long 0xFE800010
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SCR_L_A: .long 0xFE800014
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STR_U_A: .long 0xFE800018
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STR_L_A: .long 0xFE80001C
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SDR_U_A: .long 0xFE800030
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SDR_L_A: .long 0xFE800034
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EMRS_A: .long 0xFE902000
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MRS1_A: .long 0xFE900B08
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MRS2_A: .long 0xFE900308
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MIM_U_D: .long 0x00000000
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MIM_L_D0: .long 0x04100008
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MIM_L_D1: .long 0x02EE0009
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MIM_L_D2: .long 0x02EE0209
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SDR_L_A_D0: .long 0x00000300
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STR_L_A_D0: .long 0x00010040
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MIM_L_A_D1: .long 0x04100009
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SCR_L_A_D0: .long 0x00000003
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SCR_L_A_D1: .long 0x00000002
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MIM_L_A_D2: .long 0x04100209
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SCR_L_A_D2: .long 0x00000004
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SCR_L_NORMAL: .long 0x00000000
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SCR_L_NOP: .long 0x00000001
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SCR_L_PALL: .long 0x00000002
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SCR_L_CKE_EN: .long 0x00000003
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SCR_L_CBR: .long 0x00000004
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STR_L_D: .long 0x000F3980
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SDR_L_D: .long 0x00000400
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EMRS_D: .long 0x00000000
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MRS1_D: .long 0x00000000
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MRS2_D: .long 0x00000000
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/* USB */
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USB_USBHSC_A: .long 0xFFEC80F0
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USB_USBHSC_D: .long 0x00000000
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