mirror of
https://github.com/u-boot/u-boot.git
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482 lines
16 KiB
C
482 lines
16 KiB
C
/*
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* (C) Copyright 2000, 2001, 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific,
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* for SinoVee Microsystems SC8xx series SBC
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* http://www.fel.com.cn (Chinese)
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* http://www.sinovee.com (English)
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* Custom configuration */
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/* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */
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/* SC85T,SC860T, FEL8xx-AT(855T/860T) */
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/*#define CONFIG_FEL8xx_AT */
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/*#define CONFIG_LCD */
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/* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */
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/* #define CONFIG_50MHz */
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/* #define CONFIG_66MHz */
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/* #define CONFIG_75MHz */
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#define CONFIG_80MHz
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/*#define CONFIG_100MHz */
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/* #define CONFIG_BUS_DIV2 1 */
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/* for BOOT device port size */
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/* #define CONFIG_BOOT_8B */
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#define CONFIG_BOOT_16B
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/* #define CONFIG_BOOT_32B */
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/* #define CONFIG_CAN_DRIVER */
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/* #define DEBUG */
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#define CONFIG_FEC_ENET
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/* #define CONFIG_SDRAM_16M */
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#define CONFIG_SDRAM_32M
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/* #define CONFIG_SDRAM_64M */
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#define CFG_RESET_ADDRESS 0xffffffff
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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/* #define CONFIG_MPC823 1 */
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/* #define CONFIG_MPC850 1 */
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#define CONFIG_MPC855 1
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/* #define CONFIG_MPC860 1 */
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/* #define CONFIG_MPC860T 1 */
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#undef CONFIG_WATCHDOG /* watchdog */
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#define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */
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#ifdef CONFIG_LCD /* with LCD controller ? */
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/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */
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#endif
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 19200 /* console baudrate = 115kbps */
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#define CONFIG_BOARD_TYPES 1 /* support board types */
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#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"flash_nfs=run nfsargs addip;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0" \
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"rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \
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"bootfile=pImage-sc855t\0" \
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"kernel_addr=48000000\0" \
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"ramdisk_addr=48100000\0" \
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""
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#define CONFIG_BOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
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"tftpboot 0x210000 pImage-sc855t;bootm 0x210000"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#ifdef CONFIG_LCD
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# undef CONFIG_STATUS_LED /* disturbs display */
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#else
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# define CONFIG_STATUS_LED 1 /* Status LED enabled */
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#endif /* CONFIG_LCD */
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#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DOC
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#define CONFIG_CMD_DATE
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#define CFG_NAND_LEGACY
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xFF000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x40000000
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#define CFG_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_ENV_IS_IN_FLASH 1
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#ifdef CONFIG_BOOT_8B
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#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
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#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
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#elif defined (CONFIG_BOOT_16B)
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#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
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#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
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#elif defined (CONFIG_BOOT_32B)
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#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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#endif
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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/*-----------------------------------------------------------------------
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* Hardware Information Block
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*/
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#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
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#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
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#define CFG_HWINFO_MAGIC 0x46454C38 /* 'SVM8' */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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/*#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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*/
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR 0xffffff88
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#ifndef CONFIG_CAN_DRIVER
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/*#define CFG_SIUMCR 0x00610c00 */
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#define CFG_SIUMCR 0x00000000
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#else /* we must activate GPL5 in the SIUMCR for CAN */
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#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
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#endif /* CONFIG_CAN_DRIVER */
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR 0x0001
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/*-----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register 11-27
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*-----------------------------------------------------------------------
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*/
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#define CFG_RTCSC 0x00c3
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CFG_PISCR 0x0000
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit
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*/
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#if defined (CONFIG_100MHz)
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#define CFG_PLPRCR 0x06301000
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#define CONFIG_8xx_GCLK_FREQ 100000000
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#elif defined (CONFIG_80MHz)
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#define CFG_PLPRCR 0x04f01000
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#define CONFIG_8xx_GCLK_FREQ 80000000
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#elif defined(CONFIG_75MHz)
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#define CFG_PLPRCR 0x04a00100
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#define CONFIG_8xx_GCLK_FREQ 75000000
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#elif defined(CONFIG_66MHz)
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#define CFG_PLPRCR 0x04101000
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#define CONFIG_8xx_GCLK_FREQ 66000000
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#elif defined(CONFIG_50MHz)
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#define CFG_PLPRCR 0x03101000
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#define CONFIG_8xx_GCLK_FREQ 50000000
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#endif
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#ifdef CONFIG_BUS_DIV2
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#define CFG_SCCR 0x02020000 | SCCR_RTSEL
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#else /* up to 50 MHz we use a 1:1 clock */
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#define CFG_SCCR 0x02000000 | SCCR_RTSEL
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#endif
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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*-----------------------------------------------------------------------
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*
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*/
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#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
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#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
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#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
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#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_IO_ADDR (0xEC000000)
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#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
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*-----------------------------------------------------------------------
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*/
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#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
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#define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#undef CONFIG_IDE_RESET /* reset for ide not supported */
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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#define CFG_ATA_BASE_ADDR 0xFE100010
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#define CFG_ATA_IDE0_OFFSET 0x0000
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/*#define CFG_ATA_IDE1_OFFSET 0x0C00 */
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#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O
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*/
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#define CFG_ATA_REG_OFFSET 0x0200 /* Offset for normal register accesses
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*/
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#define CFG_ATA_ALT_OFFSET 0x0210 /* Offset for alternate registers
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*/
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#define CONFIG_ATAPI
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#define CFG_PIO_MODE 0
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
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/*#define CFG_DER 0x2002000F*/
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#define CFG_DER 0x0
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
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#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
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/* used to re-map FLASH both when starting from SRAM or FLASH:
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* restrict access enough to keep SRAM working (if any)
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* but not too much to meddle with FLASH accesses
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*/
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#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
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#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
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/*
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* FLASH timing:
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*/
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#if defined(CONFIG_100MHz)
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#define CFG_OR_TIMING_FLASH 0x000002f4
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#define CFG_OR_TIMING_DOC 0x000002f4
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#define CFG_MxMR_PTx 0x61000000
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#define CFG_MPTPR 0x400
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#elif defined(CONFIG_80MHz)
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#define CFG_OR_TIMING_FLASH 0x00000ff4
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#define CFG_OR_TIMING_DOC 0x000001f4
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#define CFG_MxMR_PTx 0x4e000000
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#define CFG_MPTPR 0x400
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#elif defined(CONFIG_75MHz)
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#define CFG_OR_TIMING_FLASH 0x000008f4
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#define CFG_OR_TIMING_DOC 0x000002f4
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#define CFG_MxMR_PTx 0x49000000
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#define CFG_MPTPR 0x400
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#elif defined(CONFIG_66MHz)
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#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
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OR_SCY_3_CLK | OR_EHTR | OR_BI)
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/*#define CFG_OR_TIMING_FLASH 0x000001f4 */
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#define CFG_OR_TIMING_DOC 0x000003f4
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#define CFG_MxMR_PTx 0x40000000
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#define CFG_MPTPR 0x400
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#else /* 50 MHz */
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#define CFG_OR_TIMING_FLASH 0x00000ff4
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#define CFG_OR_TIMING_DOC 0x000001f4
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#define CFG_MxMR_PTx 0x30000000
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#define CFG_MPTPR 0x400
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#endif /*CONFIG_??MHz */
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#if defined (CONFIG_BOOT_8B) /* 512K X 8 ,29F040 , 2MB space */
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#define CFG_OR0_PRELIM (0xffe00000 | CFG_OR_TIMING_FLASH)
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#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)
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#elif defined (CONFIG_BOOT_16B) /* 29lv160 X 16 , 4MB space */
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#define CFG_OR0_PRELIM (0xffc00000 | CFG_OR_TIMING_FLASH)
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#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
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#elif defined( CONFIG_BOOT_32B ) /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */
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#define CFG_OR0_PRELIM (0xfc000000 | CFG_OR_TIMING_FLASH)
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#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
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#else
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#error Boot device port size missing.
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#endif
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/*
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* Disk-On-Chip configuration
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*/
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#define CFG_DOC_SHORT_TIMEOUT
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#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
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#define CFG_DOC_SUPPORT_2000
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#define CFG_DOC_SUPPORT_MILLENNIUM
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#define CFG_DOC_BASE 0x80000000
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#endif /* __CONFIG_H */
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