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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
120 lines
2.9 KiB
C
120 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Andestech ATFTMR010 timer driver
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*
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* (C) Copyright 2016
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* Rick Chen, NDS32 Software Engineering, rick@andestech.com
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <timer.h>
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#include <linux/io.h>
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/*
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* Timer Control Register
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*/
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#define T3_UPDOWN (1 << 11)
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#define T2_UPDOWN (1 << 10)
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#define T1_UPDOWN (1 << 9)
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#define T3_OFENABLE (1 << 8)
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#define T3_CLOCK (1 << 7)
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#define T3_ENABLE (1 << 6)
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#define T2_OFENABLE (1 << 5)
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#define T2_CLOCK (1 << 4)
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#define T2_ENABLE (1 << 3)
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#define T1_OFENABLE (1 << 2)
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#define T1_CLOCK (1 << 1)
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#define T1_ENABLE (1 << 0)
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/*
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* Timer Interrupt State & Mask Registers
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*/
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#define T3_OVERFLOW (1 << 8)
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#define T3_MATCH2 (1 << 7)
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#define T3_MATCH1 (1 << 6)
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#define T2_OVERFLOW (1 << 5)
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#define T2_MATCH2 (1 << 4)
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#define T2_MATCH1 (1 << 3)
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#define T1_OVERFLOW (1 << 2)
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#define T1_MATCH2 (1 << 1)
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#define T1_MATCH1 (1 << 0)
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struct atftmr_timer_regs {
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u32 t1_counter; /* 0x00 */
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u32 t1_load; /* 0x04 */
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u32 t1_match1; /* 0x08 */
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u32 t1_match2; /* 0x0c */
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u32 t2_counter; /* 0x10 */
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u32 t2_load; /* 0x14 */
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u32 t2_match1; /* 0x18 */
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u32 t2_match2; /* 0x1c */
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u32 t3_counter; /* 0x20 */
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u32 t3_load; /* 0x24 */
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u32 t3_match1; /* 0x28 */
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u32 t3_match2; /* 0x2c */
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u32 cr; /* 0x30 */
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u32 int_state; /* 0x34 */
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u32 int_mask; /* 0x38 */
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};
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struct atftmr_timer_platdata {
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struct atftmr_timer_regs *regs;
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};
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static int atftmr_timer_get_count(struct udevice *dev, u64 *count)
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{
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struct atftmr_timer_platdata *plat = dev->platdata;
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struct atftmr_timer_regs *const regs = plat->regs;
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u32 val;
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val = readl(®s->t3_counter);
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*count = timer_conv_64(val);
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return 0;
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}
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static int atftmr_timer_probe(struct udevice *dev)
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{
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struct atftmr_timer_platdata *plat = dev->platdata;
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struct atftmr_timer_regs *const regs = plat->regs;
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u32 cr;
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writel(0, ®s->t3_load);
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writel(0, ®s->t3_counter);
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writel(TIMER_LOAD_VAL, ®s->t3_match1);
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writel(TIMER_LOAD_VAL, ®s->t3_match2);
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/* disable interrupts */
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writel(T3_MATCH1|T3_MATCH2|T3_OVERFLOW , ®s->int_mask);
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cr = readl(®s->cr);
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cr |= (T3_ENABLE|T3_UPDOWN);
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writel(cr, ®s->cr);
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return 0;
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}
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static int atftme_timer_ofdata_to_platdata(struct udevice *dev)
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{
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struct atftmr_timer_platdata *plat = dev_get_platdata(dev);
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plat->regs = map_physmem(devfdt_get_addr(dev),
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sizeof(struct atftmr_timer_regs),
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MAP_NOCACHE);
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return 0;
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}
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static const struct timer_ops ag101p_timer_ops = {
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.get_count = atftmr_timer_get_count,
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};
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static const struct udevice_id ag101p_timer_ids[] = {
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{ .compatible = "andestech,attmr010" },
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{}
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};
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U_BOOT_DRIVER(altera_timer) = {
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.name = "ag101p_timer",
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.id = UCLASS_TIMER,
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.of_match = ag101p_timer_ids,
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.ofdata_to_platdata = atftme_timer_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata),
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.probe = atftmr_timer_probe,
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.ops = &ag101p_timer_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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