mirror of
https://github.com/u-boot/u-boot.git
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0db5bca807
- Add port to MPC555/556 microcontrollers
- Add support for cmi customer board with
Intel 28F128J3A, 28F320J3A or 28F640J3A flash.
* Patch by Rick Bronson, 28 Mar 2003:
- fix common/cmd_nand.c
318 lines
8.7 KiB
Cheetah
318 lines
8.7 KiB
Cheetah
/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* This file contains all the macros and symbols which define
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* a PowerPC assembly language environment.
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*/
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#ifndef __PPC_ASM_TMPL__
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#define __PPC_ASM_TMPL__
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/***************************************************************************
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*
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* These definitions simplify the ugly declarations necessary for GOT
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* definitions.
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*
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* Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es
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*
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* Uses r14 to access the GOT
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*/
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#define START_GOT \
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.section ".got2","aw"; \
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.LCTOC1 = .+32768
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#define END_GOT \
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.text
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#define GET_GOT \
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bl 1f ; \
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.text 2 ; \
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0: .long .LCTOC1-1f ; \
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.text ; \
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1: mflr r14 ; \
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lwz r0,0b-1b(r14) ; \
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add r14,r0,r14 ;
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#define GOT_ENTRY(NAME) .L_ ## NAME = . - .LCTOC1 ; .long NAME
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#define GOT(NAME) .L_ ## NAME (r14)
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/***************************************************************************
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* Register names
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*/
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#define r0 0
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#define r1 1
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#define r2 2
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#define r3 3
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#define r4 4
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#define r5 5
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#define r6 6
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#define r7 7
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#define r8 8
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#define r9 9
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#define r10 10
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#define r11 11
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#define r12 12
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#define r13 13
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#define r14 14
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#define r15 15
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#define r16 16
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#define r17 17
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#define r18 18
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#define r19 19
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#define r20 20
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#define r21 21
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#define r22 22
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#define r23 23
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#define r24 24
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#define r25 25
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#define r26 26
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#define r27 27
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#define r28 28
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#define r29 29
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#define r30 30
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#define r31 31
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#if defined(CONFIG_8xx) || defined(CONFIG_MPC824X)
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/* Some special registers */
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#define ICR 148 /* Interrupt Cause Register (37-44) */
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#define DER 149
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#define COUNTA 150 /* Breakpoint Counter (37-44) */
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#define COUNTB 151 /* Breakpoint Counter (37-44) */
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#define LCTRL1 156 /* Load/Store Support (37-40) */
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#define LCTRL2 157 /* Load/Store Support (37-41) */
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#define ICTRL 158
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#endif /* CONFIG_8xx, CONFIG_MPC824X */
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#if defined(CONFIG_5xx)
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/* Some special purpose registers */
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#define DER 149 /* Debug Enable Register */
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#define COUNTA 150 /* Breakpoint Counter */
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#define COUNTB 151 /* Breakpoint Counter */
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#define LCTRL1 156 /* Load/Store Support */
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#define LCTRL2 157 /* Load/Store Support */
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#define ICTRL 158 /* I-Bus Support Control Register */
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#define EID 81
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#endif /* CONFIG_5xx */
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#if defined(CONFIG_8xx)
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/* Registers in the processor's internal memory map that we use.
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*/
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#define SYPCR 0x00000004
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#define BR0 0x00000100
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#define OR0 0x00000104
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#define BR1 0x00000108
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#define OR1 0x0000010c
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#define BR2 0x00000110
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#define OR2 0x00000114
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#define BR3 0x00000118
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#define OR3 0x0000011c
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#define BR4 0x00000120
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#define OR4 0x00000124
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#define MAR 0x00000164
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#define MCR 0x00000168
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#define MAMR 0x00000170
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#define MBMR 0x00000174
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#define MSTAT 0x00000178
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#define MPTPR 0x0000017a
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#define MDR 0x0000017c
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#define TBSCR 0x00000200
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#define TBREFF0 0x00000204
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#define PLPRCR 0x00000284
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#elif defined(CONFIG_8260)
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#define HID2 1011
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#define HID0_IFEM (1<<7)
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#define HID0_ICE_BITPOS 16
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#define HID0_DCE_BITPOS 17
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#define IM_REGBASE 0x10000
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#define IM_SYPCR (IM_REGBASE+0x0004)
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#define IM_SWSR (IM_REGBASE+0x000e)
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#define IM_BR0 (IM_REGBASE+0x0100)
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#define IM_OR0 (IM_REGBASE+0x0104)
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#define IM_BR1 (IM_REGBASE+0x0108)
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#define IM_OR1 (IM_REGBASE+0x010c)
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#define IM_BR2 (IM_REGBASE+0x0110)
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#define IM_OR2 (IM_REGBASE+0x0114)
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#define IM_MPTPR (IM_REGBASE+0x0184)
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#define IM_PSDMR (IM_REGBASE+0x0190)
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#define IM_PSRT (IM_REGBASE+0x019c)
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#define IM_IMMR (IM_REGBASE+0x01a8)
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#define IM_SCCR (IM_REGBASE+0x0c80)
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#endif
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#define curptr r2
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#define SYNC \
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sync; \
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isync
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/*
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* Macros for storing registers into and loading registers from
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* exception frames.
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*/
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#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
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#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
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#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
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#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
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#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
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#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
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#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
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#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
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#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
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#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
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/*
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* GCC sometimes accesses words at negative offsets from the stack
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* pointer, although the SysV ABI says it shouldn't. To cope with
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* this, we leave this much untouched space on the stack on exception
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* entry.
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*/
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#define STACK_UNDERHEAD 64
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/*
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* Exception entry code. This code runs with address translation
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* turned off, i.e. using physical addresses.
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* We assume sprg3 has the physical address of the current
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* task's thread_struct.
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*/
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#define EXCEPTION_PROLOG \
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mtspr SPRG0,r20; \
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mtspr SPRG1,r21; \
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mfcr r20; \
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subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\
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stw r20,_CCR(r21); /* save registers */ \
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stw r22,GPR22(r21); \
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stw r23,GPR23(r21); \
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mfspr r20,SPRG0; \
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stw r20,GPR20(r21); \
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mfspr r22,SPRG1; \
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stw r22,GPR21(r21); \
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mflr r20; \
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stw r20,_LINK(r21); \
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mfctr r22; \
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stw r22,_CTR(r21); \
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mfspr r20,XER; \
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stw r20,_XER(r21); \
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mfspr r22,SRR0; \
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mfspr r23,SRR1; \
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stw r0,GPR0(r21); \
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stw r1,GPR1(r21); \
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stw r2,GPR2(r21); \
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stw r1,0(r21); \
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mr r1,r21; /* set new kernel sp */ \
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SAVE_4GPRS(3, r21);
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/*
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* Note: code which follows this uses cr0.eq (set if from kernel),
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* r21, r22 (SRR0), and r23 (SRR1).
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*/
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/*
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* Critical exception entry code. This is just like the other exception
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* code except that it uses SRR2 and SRR3 instead of SRR0 and SRR1.
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*/
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#define CRITICAL_EXCEPTION_PROLOG \
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mtspr SPRG0,r20; \
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mtspr SPRG1,r21; \
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mfcr r20; \
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subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\
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stw r20,_CCR(r21); /* save registers */ \
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stw r22,GPR22(r21); \
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stw r23,GPR23(r21); \
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mfspr r20,SPRG0; \
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stw r20,GPR20(r21); \
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mfspr r22,SPRG1; \
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stw r22,GPR21(r21); \
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mflr r20; \
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stw r20,_LINK(r21); \
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mfctr r22; \
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stw r22,_CTR(r21); \
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mfspr r20,XER; \
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stw r20,_XER(r21); \
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mfspr r22,990; /* SRR2 */ \
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mfspr r23,991; /* SRR3 */ \
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stw r0,GPR0(r21); \
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stw r1,GPR1(r21); \
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stw r2,GPR2(r21); \
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stw r1,0(r21); \
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mr r1,r21; /* set new kernel sp */ \
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SAVE_4GPRS(3, r21);
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/*
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* Note: code which follows this uses cr0.eq (set if from kernel),
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* r21, r22 (SRR2), and r23 (SRR3).
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*/
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/*
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* Exception vectors.
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*
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* The data words for `hdlr' and `int_return' are initialized with
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* OFFSET values only; they must be relocated first before they can
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* be used!
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*/
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#define STD_EXCEPTION(n, label, hdlr) \
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. = n; \
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label: \
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EXCEPTION_PROLOG; \
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lwz r3,GOT(transfer_to_handler); \
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mtlr r3; \
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addi r3,r1,STACK_FRAME_OVERHEAD; \
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li r20,MSR_KERNEL; \
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rlwimi r20,r23,0,25,25; \
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blrl ; \
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.L_ ## label : \
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.long hdlr - _start + EXC_OFF_SYS_RESET; \
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.long int_return - _start + EXC_OFF_SYS_RESET
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#define CRIT_EXCEPTION(n, label, hdlr) \
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. = n; \
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label: \
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CRITICAL_EXCEPTION_PROLOG; \
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lwz r3,GOT(transfer_to_handler); \
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mtlr r3; \
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addi r3,r1,STACK_FRAME_OVERHEAD; \
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li r20,MSR_KERNEL; \
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rlwimi r20,r23,0,25,25; \
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blrl ; \
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.L_ ## label : \
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.long hdlr - _start + EXC_OFF_SYS_RESET; \
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.long crit_return - _start + EXC_OFF_SYS_RESET
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#endif /* __PPC_ASM_TMPL__ */
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