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130fbeb1c5
With d6a320d we moved some clock externs out of blackfin_local.h and
into clock.h but now need to include <asm/clock.h> in more drivers to
avoid warnings.
Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Tom Rini <trini@ti.com>
352 lines
8.8 KiB
C
352 lines
8.8 KiB
C
/*
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* video.c - run splash screen on lcd
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*
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* Copyright (c) 2007-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <stdarg.h>
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#include <common.h>
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#include <config.h>
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#include <malloc.h>
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#include <asm/blackfin.h>
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#include <asm/clock.h>
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#include <asm/gpio.h>
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#include <asm/portmux.h>
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#include <asm/mach-common/bits/dma.h>
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#include <i2c.h>
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#include <linux/types.h>
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#include <stdio_dev.h>
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#include <lzma/LzmaTypes.h>
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#include <lzma/LzmaDec.h>
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#include <lzma/LzmaTools.h>
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#define DMA_SIZE16 2
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#include <asm/mach-common/bits/eppi.h>
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#include EASYLOGO_HEADER
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#define LCD_X_RES 480 /*Horizontal Resolution */
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#define LCD_Y_RES 272 /* Vertical Resolution */
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#define LCD_BPP 24 /* Bit Per Pixel */
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#define LCD_PIXEL_SIZE (LCD_BPP / 8)
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#define DMA_BUS_SIZE 32
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#define ACTIVE_VIDEO_MEM_OFFSET 0
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/* -- Horizontal synchronizing --
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*
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* Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
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* (LCY-W-06602A Page 9 of 22)
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*
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* Clock Frequency 1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
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*
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* Period TH - 525 - Clock
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* Pulse width THp - 41 - Clock
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* Horizontal period THd - 480 - Clock
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* Back porch THb - 2 - Clock
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* Front porch THf - 2 - Clock
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*
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* -- Vertical synchronizing --
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* Period TV - 286 - Line
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* Pulse width TVp - 10 - Line
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* Vertical period TVd - 272 - Line
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* Back porch TVb - 2 - Line
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* Front porch TVf - 2 - Line
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*/
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#define LCD_CLK (8*1000*1000) /* 8MHz */
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/* # active data to transfer after Horizontal Delay clock */
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#define EPPI_HCOUNT LCD_X_RES
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/* # active lines to transfer after Vertical Delay clock */
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#define EPPI_VCOUNT LCD_Y_RES
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/* Samples per Line = 480 (active data) + 45 (padding) */
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#define EPPI_LINE 525
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/* Lines per Frame = 272 (active data) + 14 (padding) */
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#define EPPI_FRAME 286
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/* FS1 (Hsync) Width (Typical)*/
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#define EPPI_FS1W_HBL 41
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/* FS1 (Hsync) Period (Typical) */
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#define EPPI_FS1P_AVPL EPPI_LINE
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/* Horizontal Delay clock after assertion of Hsync (Typical) */
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#define EPPI_HDELAY 43
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/* FS2 (Vsync) Width = FS1 (Hsync) Period * 10 */
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#define EPPI_FS2W_LVB (EPPI_LINE * 10)
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/* FS2 (Vsync) Period = FS1 (Hsync) Period * Lines per Frame */
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#define EPPI_FS2P_LAVF (EPPI_LINE * EPPI_FRAME)
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/* Vertical Delay after assertion of Vsync (2 Lines) */
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#define EPPI_VDELAY 12
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#define EPPI_CLIP 0xFF00FF00
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/* EPPI Control register configuration value for RGB out
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* - EPPI as Output
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* GP 2 frame sync mode,
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* Internal Clock generation disabled, Internal FS generation enabled,
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* Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
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* FS1 & FS2 are active high,
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* DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
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* DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
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* Swapping Enabled,
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* One (DMA) Channel Mode,
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* RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
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* Regular watermark - when FIFO is 100% full,
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* Urgent watermark - when FIFO is 75% full
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*/
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#define EPPI_CONTROL (0x20136E2E)
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static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
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{
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u32 sclk = get_sclk();
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/* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
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return (((sclk / target_ppi_clk) / 2) - 1);
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}
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void Init_PPI(void)
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{
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u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
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bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
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bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
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bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
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bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
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bfin_write_EPPI0_CLIP(EPPI_CLIP);
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bfin_write_EPPI0_FRAME(EPPI_FRAME);
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bfin_write_EPPI0_LINE(EPPI_LINE);
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bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
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bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
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bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
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bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
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bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
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/*
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* DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
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* RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
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*/
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#if defined(CONFIG_VIDEO_RGB666)
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bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
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RGB_FMT_EN);
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#else
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bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
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~RGB_FMT_EN);
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#endif
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}
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#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
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void Init_DMA(void *dst)
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{
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#if defined(CONFIG_DEB_DMA_URGENT)
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bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT);
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#endif
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bfin_write_DMA12_START_ADDR(dst);
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/* X count */
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bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
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bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8);
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/* Y count */
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bfin_write_DMA12_Y_COUNT(LCD_Y_RES);
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bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8);
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/* DMA Config */
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bfin_write_DMA12_CONFIG(
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WDSIZE_32 | /* 32 bit DMA */
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DMA2D | /* 2D DMA */
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FLOW_AUTO /* autobuffer mode */
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);
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}
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void Init_Ports(void)
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{
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const unsigned short pins[] = {
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P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
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P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9,
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P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
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P_PPI0_D15, P_PPI0_D16, P_PPI0_D17,
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#if !defined(CONFIG_VIDEO_RGB666)
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P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22,
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P_PPI0_D23,
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#endif
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P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0,
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};
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peripheral_request_list(pins, "lcd");
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gpio_request(GPIO_PE3, "lcd-disp");
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gpio_direction_output(GPIO_PE3, 1);
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}
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void EnableDMA(void)
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{
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bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN);
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}
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void DisableDMA(void)
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{
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bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN);
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}
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/* enable and disable PPI functions */
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void EnablePPI(void)
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{
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bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
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}
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void DisablePPI(void)
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{
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bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
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}
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int video_init(void *dst)
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{
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Init_Ports();
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Init_DMA(dst);
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EnableDMA();
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Init_PPI();
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EnablePPI();
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return 0;
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}
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void video_stop(void)
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{
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DisablePPI();
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DisableDMA();
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}
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static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
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{
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if (dcache_status())
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blackfin_dcache_flush_range(logo->data,
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logo->data + logo->size);
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bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
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/* Setup destination start address */
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bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
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+ (y * LCD_X_RES * LCD_PIXEL_SIZE));
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/* Setup destination xcount */
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bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
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/* Setup destination xmodify */
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bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
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/* Setup destination ycount */
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bfin_write_MDMA_D0_Y_COUNT(logo->height);
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/* Setup destination ymodify */
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bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE +
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DMA_SIZE16);
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/* Setup Source start address */
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bfin_write_MDMA_S0_START_ADDR(logo->data);
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/* Setup Source xcount */
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bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
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/* Setup Source xmodify */
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bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
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/* Setup Source ycount */
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bfin_write_MDMA_S0_Y_COUNT(logo->height);
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/* Setup Source ymodify */
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bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
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/* Enable source DMA */
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bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
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SSYNC();
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bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
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while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN) ;
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bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE
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| DMA_ERR);
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bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE
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| DMA_ERR);
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}
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void video_putc(const char c)
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{
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}
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void video_puts(const char *s)
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{
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}
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int drv_video_init(void)
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{
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int error, devices = 1;
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struct stdio_dev videodev;
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u8 *dst;
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u32 fbmem_size =
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LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
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dst = malloc(fbmem_size);
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if (dst == NULL) {
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printf("Failed to alloc FB memory\n");
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return -1;
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}
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#ifdef EASYLOGO_ENABLE_GZIP
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unsigned char *data = EASYLOGO_DECOMP_BUFFER;
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unsigned long src_len = EASYLOGO_ENABLE_GZIP;
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error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len);
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bfin_logo.data = data;
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#elif defined(EASYLOGO_ENABLE_LZMA)
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unsigned char *data = EASYLOGO_DECOMP_BUFFER;
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SizeT lzma_len = bfin_logo.size;
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error = lzmaBuffToBuffDecompress(data, &lzma_len,
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bfin_logo.data, EASYLOGO_ENABLE_LZMA);
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bfin_logo.data = data;
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#else
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error = 0;
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#endif
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if (error) {
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puts("Failed to decompress logo\n");
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free(dst);
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return -1;
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}
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memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0],
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fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
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dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
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(LCD_X_RES - bfin_logo.width) / 2,
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(LCD_Y_RES - bfin_logo.height) / 2);
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video_init(dst); /* Video initialization */
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memset(&videodev, 0, sizeof(videodev));
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strcpy(videodev.name, "video");
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videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
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videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
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videodev.putc = video_putc; /* 'putc' function */
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videodev.puts = video_puts; /* 'puts' function */
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error = stdio_register(&videodev);
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return (error == 0) ? devices : error;
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}
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