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5a95f6fbd2
Add standalone application to change SMC91C111 MAC addresses, see examples/README.smc91111_eeprom * Patch by Xiaogeng (Shawn) Jin, 12 Oct 2004: Fix Flash support for ARM Integrator CP.
275 lines
9.0 KiB
C
275 lines
9.0 KiB
C
/*
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* (C) Copyright 2004
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* Texas Instruments.
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* Richard Woodruff <r-woodruff2@ti.com>
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* Kshitij Gupta <kshitij@ti.com>
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*
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* Configuration settings for the 242x TI H4 board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
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#define CONFIG_OMAP 1 /* in a TI OMAP core */
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#define CONFIG_OMAP2420 1 /* which is in a 2420 */
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#define CONFIG_OMAP2420H4 1 /* and on a H4 board */
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/*#define CONFIG_APTIX 1 #* define if on APTIX test chip */
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/*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */
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/* Clock config to target*/
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#define PRCM_CONFIG_II 1
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/*#define PRCM_CONFIG_III 1 */
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/* Memory configuration on board */
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/*#define CONFIG_OPTIMIZE_DDR 1 */
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#include <asm/arch/omap2420.h> /* get chip and board defs */
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/* On H4, NOR and NAND flash are mutual exclusive.
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Define this if you want to use NAND
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*/
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/*#define CFG_NAND_BOOT */
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#ifdef CONFIG_APTIX
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#define V_SCLK 1500000
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#else
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#define V_SCLK 12000000
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#endif
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/* input clock of PLL */
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/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
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#define CONFIG_SYS_CLK_FREQ V_SCLK
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#undef CONFIG_USE_IRQ /* no support for IRQs */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_REVISION_TAG 1
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/*
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* Size of malloc() pool
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*/
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#define CFG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K)
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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/*
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* Hardware drivers
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*/
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/*
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* SMC91c96 Etherent
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*/
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#define CONFIG_DRIVER_LAN91C96
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#define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300)
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#define CONFIG_LAN91C96_EXT_PHY
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/*
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* NS16550 Configuration
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*/
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#ifdef CONFIG_APTIX
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#define V_NS16550_CLK (6000000) /* 6MHz in current MaxSet */
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#else
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#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
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#endif
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE (-4)
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#define CFG_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */
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#define CFG_NS16550_COM1 OMAP2420_UART1
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/*
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* select serial console configuration
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*/
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#define CONFIG_SERIAL1 1 /* UART1 on H4 */
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C
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#define CFG_I2C_SPEED 100000
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#define CFG_I2C_SLAVE 1
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#define CONFIG_DRIVER_OMAP24XX_I2C
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
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#ifdef CFG_NAND_BOOT
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_NAND | CFG_CMD_JFFS2)
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#else
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2)
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#endif
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/* I'd like to get to these. Snap kernel loads if we make MMC go */
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/* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_DHCP | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_I2C) */
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#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Board NAND Info.
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*/
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#define CFG_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/
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#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define SECTORSIZE 512
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define NAND_ChipID_UNKNOWN 0x00
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#define NAND_MAX_FLOORS 1
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#define NAND_MAX_CHIPS 1
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#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0)
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#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0)
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#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0)
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#define READ_NAND(adr) (*(volatile u16 *)0x6800A084)
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#define NAND_WAIT_READY(nand) udelay(10)
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#define NAND_NO_RB 1
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#define CFG_NAND_WP
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#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
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#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
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#define NAND_CTL_CLRALE(nandptr)
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#define NAND_CTL_SETALE(nandptr)
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#define NAND_CTL_CLRCLE(nandptr)
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#define NAND_CTL_SETCLE(nandptr)
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#define NAND_DISABLE_CE(nand)
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#define NAND_ENABLE_CE(nand)
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#define CONFIG_BOOTDELAY 3
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#ifdef NFS_BOOT_DEFAULTS
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#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp"
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#else
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#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
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#endif
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#define CONFIG_NETMASK 255.255.254.0
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#define CONFIG_IPADDR 128.247.77.90
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#define CONFIG_SERVERIP 128.247.77.158
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#define CONFIG_BOOTFILE "uImage"
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/*
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* Miscellaneous configurable options
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*/
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#ifdef CONFIG_APTIX
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#define V_PROMPT "OMAP2420 Aptix # "
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#else
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#define V_PROMPT "OMAP242x H4 # "
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#endif
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT V_PROMPT
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */
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#define CFG_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#define CFG_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */
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/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
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* 32KHz clk, or from external sig. This rate is divided by a local divisor.
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*/
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#ifdef CONFIG_APTIX
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#define V_PVT 3
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#else
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#define V_PVT 7 /* use with 12MHz/128 */
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#endif
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#define CFG_TIMERBASE OMAP2420_GPT2
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#define CFG_PVT V_PVT /* 2^(pvt+1) */
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#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE SZ_128K /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
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#endif
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0
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#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
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#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
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#define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */
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#define PHYS_FLASH_SIZE_1 SZ_32M
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#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
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#define PHYS_FLASH_SIZE_2 SZ_32M
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#define CFG_FLASH_BASE PHYS_FLASH_1
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
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#ifdef CFG_NAND_BOOT
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#define CFG_ENV_IS_IN_NAND 1
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#define CFG_ENV_OFFSET 0x80000 /* environment starts here */
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#else
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + SZ_128K)
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#define CFG_ENV_IS_IN_FLASH 1
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#endif
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/* timeout values are in ticks */
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#define CFG_FLASH_ERASE_TOUT (30*75*CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (30*75*CFG_HZ) /* Timeout for Flash Write */
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/* Flash banks JFFS2 should use */
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#define CFG_MAX_MTD_BANKS (CFG_MAX_FLASH_BANKS+CFG_MAX_NAND_DEVICE)
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#define CFG_JFFS2_MEM_NAND
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#define CFG_JFFS2_FIRST_BANK 1 /* use flash_info[1] */
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#define CFG_JFFS2_NUM_BANKS 1
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#endif /* __CONFIG_H */
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