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https://github.com/u-boot/u-boot.git
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e2ffd59b4d
* Cleanup confusing use of CONFIG_ETH*ADDR - ust his only to pre-define a MAC address; use CONFIG_HAS_ETH* to enable support for additional ethernet addresses. * Cleanup drivers/i82365.c - avoid duplication of code * Fix bogus "cannot span across banks" flash error message * Add support for CompactFlash for the CPC45 Board.
347 lines
12 KiB
C
347 lines
12 KiB
C
/*
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* Copyright (C) 2004 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*
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* Support for Interphase iSPAN Communications Controllers
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* (453x and others). Tested on 4532.
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*
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* Derived from iSPAN 4539 port (iphase4539) by
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* Wolfgang Grandegger <wg@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_MPC8260 /* This is an MPC8260 CPU */
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#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */
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/*-----------------------------------------------------------------------
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* Select serial console configuration
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*
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* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*
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* If CONFIG_CONS_NONE is defined, then the serial console routines must be
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* defined elsewhere (for example, on the cogent platform, there are serial
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* ports on the motherboard which are used for the serial console - see
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* cogent/cma101/serial.[ch]).
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*/
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#define CONFIG_CONS_ON_SMC /* Define if console on SMC */
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#undef CONFIG_CONS_ON_SCC /* Define if console on SCC */
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#undef CONFIG_CONS_NONE /* Define if console on something else */
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#define CONFIG_CONS_INDEX 1 /* Which serial channel for console */
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/*-----------------------------------------------------------------------
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* Select Ethernet configuration
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*
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* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
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* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
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* for FCC).
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*
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* If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
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* be defined elsewhere (as for the console), or CFG_CMD_NET must be removed
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* from CONFIG_COMMANDS to remove support for networking.
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*/
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#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */
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#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */
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#undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */
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#define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */
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#ifdef CONFIG_ETHER_ON_FCC
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#if CONFIG_ETHER_INDEX == 3
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#define CFG_PHY_ADDR 0
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#define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
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#define CFG_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
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#endif /* CONFIG_ETHER_INDEX == 3 */
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#define CFG_CPMFCR_RAMTYPE 0
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#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
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#define CONFIG_MII /* MII PHY management */
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#define CONFIG_BITBANGMII /* Bit-bang MII PHY management */
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/*
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* GPIO pins used for bit-banged MII communications
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*/
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#define MDIO_PORT 3 /* Port D */
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#define CFG_MDIO_PIN 0x00040000 /* PD13 */
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#define CFG_MDC_PIN 0x00080000 /* PD12 */
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#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN)
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#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN)
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#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0)
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#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \
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else iop->pdat &= ~CFG_MDIO_PIN
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#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \
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else iop->pdat &= ~CFG_MDC_PIN
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#define MIIDELAY udelay(1)
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#endif /* CONFIG_ETHER_ON_FCC */
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#define CONFIG_8260_CLKIN 65536000 /* in Hz */
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#define CONFIG_BAUDRATE 38400
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \
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| CFG_CMD_ASKENV \
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| CFG_CMD_DHCP \
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| CFG_CMD_ECHO \
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| CFG_CMD_IMMAP \
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| CFG_CMD_MII \
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| CFG_CMD_PING \
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| CFG_CMD_REGINFO \
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)
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/* This must be included AFTER the definition of CONFIG_COMMANDS */
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */
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#define CONFIG_BOOTARGS "root=/dev/ram rw"
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#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
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#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
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/*-----------------------------------------------------------------------
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* Miscellaneous configurable options
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*/
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#define CFG_LONGHELP /* #undef to save memory */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* Max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */
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#define CFG_LOAD_ADDR 0x100000 /* Default load address */
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#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CFG_RESET_ADDRESS 0x09900000
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#define CONFIG_MISC_INIT_R /* We need misc_init_r() */
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/*-----------------------------------------------------------------------
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#ifdef CONFIG_BZIP2
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#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
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#else
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
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#endif /* CONFIG_BZIP2 */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_FLASH_BASE 0xFE000000
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CFG_MAX_FLASH_BANKS 1 /* Max num of memory banks */
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#define CFG_MAX_FLASH_SECT 142 /* Max num of sects on one chip */
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/* Environment is in flash, there is little space left in Serial EEPROM */
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#define CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
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#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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/*-----------------------------------------------------------------------
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* Hard Reset Configuration Words
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*
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* If you change bits in the HRCW, you must also change the CFG_*
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* defines for the various registers affected by the HRCW e.g. changing
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* HRCW_DPPCxx requires you to also change CFG_SIUMCR.
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*/
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/* 0x1686B245 */
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#define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 | HRCW_CIP |\
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HRCW_L2CPC10 | HRCW_ISB110 |\
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HRCW_BMS | HRCW_MMR11 | HRCW_APPC10 |\
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HRCW_CS10PC01 | HRCW_MODCK_H0101 \
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)
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/* No slaves */
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#define CFG_HRCW_SLAVE1 0
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#define CFG_HRCW_SLAVE2 0
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#define CFG_HRCW_SLAVE3 0
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#define CFG_HRCW_SLAVE4 0
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#define CFG_HRCW_SLAVE5 0
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#define CFG_HRCW_SLAVE6 0
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#define CFG_HRCW_SLAVE7 0
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xF0F00000
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#ifdef CFG_REV_B
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#define CFG_DEFAULT_IMMR 0xFF000000
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#endif /* CFG_REV_B */
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
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/*-----------------------------------------------------------------------
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* HIDx - Hardware Implementation-dependent Registers 2-11
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*-----------------------------------------------------------------------
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* HID0 also contains cache control.
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*
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* HID1 has only read-only information - nothing to set.
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*/
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#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
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HID0_IFEM|HID0_ABE)
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#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
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#define CFG_HID2 0
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/*-----------------------------------------------------------------------
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* RMR - Reset Mode Register 5-5
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*-----------------------------------------------------------------------
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* turn on Checkstop Reset Enable
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*/
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#define CFG_RMR RMR_CSRE
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/*-----------------------------------------------------------------------
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* BCR - Bus Configuration 4-25
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*-----------------------------------------------------------------------
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*/
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#define CFG_BCR 0xA01C0000
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 4-31
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*-----------------------------------------------------------------------
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*/
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#define CFG_SIUMCR 0x42250000/* 0x4205C000 */
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 4-35
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
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*/
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#if defined (CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
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SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
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#else
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#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
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SYPCR_SWRI|SYPCR_SWP)
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#endif /* CONFIG_WATCHDOG */
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/*-----------------------------------------------------------------------
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* TMCNTSC - Time Counter Status and Control 4-40
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* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
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* and enable Time Counter
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*-----------------------------------------------------------------------
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*/
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#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 4-42
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
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* Periodic timer
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*/
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#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock Control 9-8
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*-----------------------------------------------------------------------
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* Ensure DFBRG is Divide by 16
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*/
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#define CFG_SCCR SCCR_DFBRG01
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/*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration 13-7
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*-----------------------------------------------------------------------
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*/
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#define CFG_RCCR 0
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/*-----------------------------------------------------------------------
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* Init Memory Controller:
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*
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* Bank Bus Machine PortSize Device
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* ---- --- ------- ----------------------------- ------
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* 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash
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* 1 60x SDRAM 64 bit SDRAM
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* 2 Local SDRAM 32 bit SDRAM
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*/
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#define CFG_USE_FIRMWARE /* If defined - do not initialise memory
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controller, rely on initialisation
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performed by the Interphase boot firmware.
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*/
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#define CFG_OR0_PRELIM 0xFE000882
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#ifdef CFG_REV_B
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#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BRx_PS_8 | BRx_V)
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#else /* Rev. D */
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#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BRx_PS_16 | BRx_V)
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#endif /* CFG_REV_B */
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#define CFG_MPTPR 0x7F00
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/* Please note that 60x SDRAM MUST start at 0 */
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_60x_BR 0x00000041
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#define CFG_60x_OR 0xF0002CD0
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#define CFG_PSDMR 0x0049929A
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#define CFG_PSRT 0x07
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#define CFG_LSDRAM_BASE 0xF7000000
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#define CFG_LOC_BR 0x00001861
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#define CFG_LOC_OR 0xFF803280
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#define CFG_LSDMR 0x8285A552
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#define CFG_LSRT 0x07
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#endif /* __CONFIG_H */
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