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288 lines
4.7 KiB
ArmAsm
288 lines
4.7 KiB
ArmAsm
/*
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* Memory sub-system initialization code for INCA-IP development board.
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*
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <asm/regdef.h>
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#define EBU_MODUL_BASE 0xB8000200
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#define EBU_CLC(value) 0x0000(value)
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#define EBU_CON(value) 0x0010(value)
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#define EBU_ADDSEL0(value) 0x0020(value)
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#define EBU_ADDSEL1(value) 0x0024(value)
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#define EBU_ADDSEL2(value) 0x0028(value)
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#define EBU_BUSCON0(value) 0x0060(value)
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#define EBU_BUSCON1(value) 0x0064(value)
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#define EBU_BUSCON2(value) 0x0068(value)
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#define MC_MODUL_BASE 0xBF800000
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#define MC_ERRCAUSE(value) 0x0100(value)
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#define MC_ERRADDR(value) 0x0108(value)
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#define MC_IOGP(value) 0x0800(value)
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#define MC_SELFRFSH(value) 0x0A00(value)
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#define MC_CTRLENA(value) 0x1000(value)
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#define MC_MRSCODE(value) 0x1008(value)
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#define MC_CFGDW(value) 0x1010(value)
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#define MC_CFGPB0(value) 0x1018(value)
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#define MC_LATENCY(value) 0x1038(value)
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#define MC_TREFRESH(value) 0x1040(value)
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#define CGU_MODUL_BASE 0xBF107000
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#define CGU_PLL1CR(value) 0x0008(value)
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#define CGU_DIVCR(value) 0x0010(value)
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#define CGU_MUXCR(value) 0x0014(value)
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#define CGU_PLL1SR(value) 0x000C(value)
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.set noreorder
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/*
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* void ebu_init(long)
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*
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* a0 has the clock value we are going to run at
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*/
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.globl ebu_init
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.ent ebu_init
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ebu_init:
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__ebu_init:
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li t1, EBU_MODUL_BASE
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li t2, 0xA0000041
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sw t2, EBU_ADDSEL0(t1)
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li t2, 0xA0800041
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sw t2, EBU_ADDSEL2(t1)
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li t2, 0xBE0000F1
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sw t2, EBU_ADDSEL1(t1)
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li t3, 100000000
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beq a0, t3, 1f
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nop
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li t3, 133000000
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beq a0, t3, 2f
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nop
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li t3, 150000000
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beq a0, t3, 2f
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nop
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b 3f
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nop
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/* 100 MHz */
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1:
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li t2, 0x8841417D
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sw t2, EBU_BUSCON0(t1)
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sw t2, EBU_BUSCON2(t1)
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li t2, 0x684142BD
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b 3f
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sw t2, EBU_BUSCON1(t1) /* delay slot */
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/* 133 or 150 MHz */
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2:
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li t2, 0x8841417E
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sw t2, EBU_BUSCON0(t1)
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sw t2, EBU_BUSCON2(t1)
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li t2, 0x684143FD
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sw t2, EBU_BUSCON1(t1)
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3:
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jr ra
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nop
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.end ebu_init
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/*
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* void cgu_init(long)
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*
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* a0 has the clock value
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*/
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.globl cgu_init
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.ent cgu_init
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cgu_init:
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__cgu_init:
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li t1, CGU_MODUL_BASE
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li t3, 100000000
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beq a0, t3, 1f
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nop
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li t3, 133000000
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beq a0, t3, 2f
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nop
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li t3, 150000000
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beq a0, t3, 3f
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nop
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b 5f
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nop
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/* 100 MHz clock */
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1:
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li t2, 0x80000014
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sw t2, CGU_DIVCR(t1)
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li t2, 0x80000000
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sw t2, CGU_MUXCR(t1)
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li t2, 0x800B0001
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b 5f
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sw t2, CGU_PLL1CR(t1) /* delay slot */
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/* 133 MHz clock */
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2:
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li t2, 0x80000054
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sw t2, CGU_DIVCR(t1)
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li t2, 0x80000000
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sw t2, CGU_MUXCR(t1)
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li t2, 0x800B0001
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b 5f
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sw t2, CGU_PLL1CR(t1) /* delay slot */
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/* 150 MHz clock */
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3:
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li t2, 0x80000017
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sw t2, CGU_DIVCR(t1)
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li t2, 0xC00B0001
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sw t2, CGU_PLL1CR(t1)
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li t3, 0x80000000
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4:
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lw t2, CGU_PLL1SR(t1)
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and t2, t2, t3
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beq t2, zero, 4b
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nop
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li t2, 0x80000001
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sw t2, CGU_MUXCR(t1)
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5:
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jr ra
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nop
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.end cgu_init
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/*
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* void sdram_init(long)
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*
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* a0 has the clock value
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*/
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.globl sdram_init
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.ent sdram_init
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sdram_init:
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__sdram_init:
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li t1, MC_MODUL_BASE
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#if 0
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/* Disable memory controller before changing any of its registers */
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sw zero, MC_CTRLENA(t1)
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#endif
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li t2, 100000000
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beq a0, t2, 1f
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nop
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li t2, 133000000
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beq a0, t2, 2f
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nop
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li t2, 150000000
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beq a0, t2, 3f
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nop
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b 5f
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nop
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/* 100 MHz clock */
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1:
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/* Set clock ratio (clkrat=1:1, rddel=3) */
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li t2, 0x00000003
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sw t2, MC_IOGP(t1)
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/* Set sdram refresh rate (4K/64ms @ 100MHz) */
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li t2, 0x0000061A
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b 4f
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sw t2, MC_TREFRESH(t1)
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/* 133 MHz clock */
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2:
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/* Set clock ratio (clkrat=1:1, rddel=3) */
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li t2, 0x00000003
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sw t2, MC_IOGP(t1)
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/* Set sdram refresh rate (4K/64ms @ 133MHz) */
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li t2, 0x00000822
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b 4f
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sw t2, MC_TREFRESH(t1)
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/* 150 MHz clock */
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3:
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/* Set clock ratio (clkrat=3:2, rddel=4) */
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li t2, 0x00000014
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sw t2, MC_IOGP(t1)
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/* Set sdram refresh rate (4K/64ms @ 150MHz) */
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li t2, 0x00000927
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sw t2, MC_TREFRESH(t1)
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4:
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/* Clear Error log registers */
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sw zero, MC_ERRCAUSE(t1)
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sw zero, MC_ERRADDR(t1)
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/* Clear Power-down registers */
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sw zero, MC_SELFRFSH(t1)
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/* Set CAS Latency */
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li t2, 0x00000020 /* CL = 2 */
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sw t2, MC_MRSCODE(t1)
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/* Set word width to 16 bit */
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li t2, 0x2
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sw t2, MC_CFGDW(t1)
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/* Set CS0 to SDRAM parameters */
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li t2, 0x000014C9
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sw t2, MC_CFGPB0(t1)
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/* Set SDRAM latency parameters */
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li t2, 0x00026325 /* BC PC100 */
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sw t2, MC_LATENCY(t1)
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5:
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/* Finally enable the controller */
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li t2, 0x00000001
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sw t2, MC_CTRLENA(t1)
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jr ra
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nop
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.end sdram_init
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.globl lowlevel_init
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.ent lowlevel_init
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lowlevel_init:
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/* Disable Watchdog.
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*/
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la t9, disable_incaip_wdt
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jalr t9
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nop
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/* EBU, CGU and SDRAM Initialization.
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*/
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li a0, CONFIG_CPU_CLOCK_RATE
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move t0, ra
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/* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
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* modify t0 and a0.
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*/
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bal __cgu_init
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nop
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bal __ebu_init
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nop
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bal __sdram_init
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nop
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move ra, t0
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jr ra
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nop
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.end lowlevel_init
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