mirror of
https://github.com/u-boot/u-boot.git
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8bc4ee9e82
Adds new board SMDKC100 that uses s5pc100 SoC Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
198 lines
4.4 KiB
ArmAsm
198 lines
4.4 KiB
ArmAsm
/*
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* Originates from Samsung's u-boot 1.1.6 port to S5PC1xx
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*
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* Copyright (C) 2009 Samsung Electrnoics
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* Inki Dae <inki.dae@samsung.com>
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* Heungjun Kim <riverful.kim@samsung.com>
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* Minkyu Kang <mk7.kang@samsung.com>
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* Kyungmin Park <kyungmin.park@samsung.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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.globl mem_ctrl_asm_init
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mem_ctrl_asm_init:
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ldr r6, =S5PC100_DMC_BASE @ 0xE6000000
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/* DLL parameter setting */
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ldr r1, =0x50101000
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str r1, [r6, #0x018] @ PHYCONTROL0
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ldr r1, =0xf4
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str r1, [r6, #0x01C] @ PHYCONTROL1
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ldr r1, =0x0
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str r1, [r6, #0x020] @ PHYCONTROL2
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/* DLL on */
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ldr r1, =0x50101002
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str r1, [r6, #0x018] @ PHYCONTROL0
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/* DLL start */
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ldr r1, =0x50101003
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str r1, [r6, #0x018] @ PHYCONTROL0
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/* Force value locking for DLL off */
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str r1, [r6, #0x018] @ PHYCONTROL0
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/* DLL off */
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ldr r1, =0x50101001
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str r1, [r6, #0x018] @ PHYCONTROL0
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/* auto refresh off */
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ldr r1, =0xff001010
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str r1, [r6, #0x000] @ CONCONTROL
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/*
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* Burst Length 4, 2 chips, 32-bit, LPDDR
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* OFF: dynamic self refresh, force precharge, dynamic power down off
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*/
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ldr r1, =0x00212100
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str r1, [r6, #0x004] @ MEMCONTROL
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/*
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* Note:
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* If Bank0 has OneDRAM we place it at 0x2800'0000
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* So finally Bank1 should address start at at 0x2000'0000
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*/
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mov r4, #0x0
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swap_memory:
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/*
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* Bank0
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* 0x30 -> 0x30000000
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* 0xf8 -> 0x37FFFFFF
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* [15:12] 0: Linear
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* [11:8 ] 2: 9 bits
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* [ 7:4 ] 2: 14 bits
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* [ 3:0 ] 2: 4 banks
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*/
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ldr r1, =0x30f80222
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/* if r4 is 1, swap the bank */
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cmp r4, #0x1
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orreq r1, r1, #0x08000000
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str r1, [r6, #0x008] @ MEMCONFIG0
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/*
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* Bank1
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* 0x38 -> 0x38000000
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* 0xf8 -> 0x3fFFFFFF
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* [15:12] 0: Linear
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* [11:8 ] 2: 9 bits
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* [ 7:4 ] 2: 14 bits
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* [ 3:0 ] 2: 4 banks
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*/
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ldr r1, =0x38f80222
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/* if r4 is 1, swap the bank */
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cmp r4, #0x1
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biceq r1, r1, #0x08000000
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str r1, [r6, #0x00c] @ MEMCONFIG1
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ldr r1, =0x20000000
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str r1, [r6, #0x014] @ PRECHCONFIG
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/*
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* FIXME: Please verify these values
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* 7.8us * 166MHz %LE %LONG1294(0x50E)
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* 7.8us * 133MHz %LE %LONG1038(0x40E),
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* 7.8us * 100MHz %LE %LONG780(0x30C),
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* 7.8us * 20MHz %LE %LONG156(0x9C),
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* 7.8us * 10MHz %LE %LONG78(0x4E)
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*/
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ldr r1, =0x0000050e
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str r1, [r6, #0x030] @ TIMINGAREF
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/* 166 MHz */
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ldr r1, =0x0c233287
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str r1, [r6, #0x034] @ TIMINGROW
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/* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */
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ldr r1, =0x32330303
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str r1, [r6, #0x038] @ TIMINGDATA
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/* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */
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ldr r1, =0x04141433
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str r1, [r6, #0x03C] @ TIMINGPOWER
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/* chip0 Deselect */
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ldr r1, =0x07000000
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str r1, [r6, #0x010] @ DIRECTCMD
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/* chip0 PALL */
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ldr r1, =0x01000000
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str r1, [r6, #0x010] @ DIRECTCMD
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/* chip0 REFA */
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ldr r1, =0x05000000
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str r1, [r6, #0x010] @ DIRECTCMD
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/* chip0 REFA */
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str r1, [r6, #0x010] @ DIRECTCMD
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/* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */
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ldr r1, =0x00000032
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str r1, [r6, #0x010] @ DIRECTCMD
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/* chip1 Deselect */
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ldr r1, =0x07100000
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str r1, [r6, #0x010] @ DIRECTCMD
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/* chip1 PALL */
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ldr r1, =0x01100000
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str r1, [r6, #0x010] @ DIRECTCMD
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/* chip1 REFA */
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ldr r1, =0x05100000
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str r1, [r6, #0x010] @ DIRECTCMD
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/* chip1 REFA */
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str r1, [r6, #0x010] @ DIRECTCMD
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/* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */
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ldr r1, =0x00100032
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str r1, [r6, #0x010] @ DIRECTCMD
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/* auto refresh on */
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ldr r1, =0xff002030
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str r1, [r6, #0x000] @ CONCONTROL
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/* PwrdnConfig */
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ldr r1, =0x00100002
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str r1, [r6, #0x028] @ PWRDNCONFIG
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/* BL%LE %LONG */
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ldr r1, =0xff212100
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str r1, [r6, #0x004] @ MEMCONTROL
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/* Try to test memory area */
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cmp r4, #0x1
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beq 1f
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mov r4, #0x1
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ldr r1, =0x37ffff00
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str r4, [r1]
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str r4, [r1, #0x4] @ dummy write
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ldr r0, [r1]
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cmp r0, r4
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bne swap_memory
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1:
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mov pc, lr
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.ltorg
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