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Add documents to describe NX25 and AE250. Also update other documents for RISC-V. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
47 lines
1.2 KiB
Plaintext
47 lines
1.2 KiB
Plaintext
NX25 is Andes CPU IP to adopt RISC-V architecture.
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Features
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========
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CPU Core
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- 5-stage in-order execution pipeline
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- Hardware Multiplier
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- radix-2/radix-4/radix-16/radix-256/fast
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- Hardware Divider
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- Optional branch prediction
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- Machine mode and optional user mode
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- Optional performance monitoring
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ISA
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- RV64I base integer instructions
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- RVC for 16-bit compressed instructions
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- RVM for multiplication and division instructions
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Memory subsystem
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- I & D local memory
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- Size: 4KB to 16MB
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- Memory subsyetem soft-error protection
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- Protection scheme: parity-checking or error-checking-and-correction (ECC)
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- Automatic hardware error correction
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Bus
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- Interface Protocol
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- Synchronous AHB (32-bit/64-bit data-width), or
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- Synchronous AXI4 (64-bit data-width)
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Power management
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- Wait for interrupt (WFI) mode
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Debug
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- Configurable number of breakpoints: 2/4/8
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- External Debug Module
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- AHB slave port
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- External JTAG debug transport module
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Platform Level Interrupt Controller (PLIC)
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- AHB slave port
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- Configurable number of interrupts: 1-1023
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- Configurable number of interrupt priorities: 3/7/15/63/127/255
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- Configurable number of targets: 1-16
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- Preempted interrupt priority stack
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