u-boot/arch/arm/cpu/armv8/fsl-layerscape
Tom Rini 720620e691 Prepare v2021.01-rc5
-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAl/0YVIACgkQFHw5/5Y0
 tywtEwv/cJWlKgcSnYjuJrxwuJdauUTfXdbUgtCxOtBw/BP4dsKkbGTJPw5q5M+4
 LJJSKyksmJVTX26h1dpkzQjOpWtTDnWqm5CTIxD52oQD7pxK+zCQ9T6S+QbQD0Se
 ogHmZluzFoluxbNgo8tiO52xvMhDO3TVAzxsNDdGfkd5/tAXOHClPc34RmAkdRHU
 VsR89AKdT2q543fiUfrRZYDzdctaNWhRGXMDcJ4+QU/8hQhrpcr8EtHbF+3mWX4K
 pA01pDz150Rn4UI6S2xKEWrjSTHe55fxVj/Qj0rq9z2E/+NqGXemf5s13AR0G/z3
 PqHdVLHzDe64pbOvmyU1pVQ0aMb8vMJUnqx68SQZY3On2c+MjRWQ+7aVVaKOcPGp
 uatk6QMrggHp3Li+3yZrLBE0qPr/sNMVb7mUesdZb6lFd2VIs8siwhfeGXMS+nDI
 xePzsR43Fnn5Q5KIqqvcWUb+TTTqUDUff0wyAU8NBgCaIBIZK8h2ppS1jjnbms0I
 mr8Er2vb
 =Dfum
 -----END PGP SIGNATURE-----

Merge tag 'v2021.01-rc5' into next

Prepare v2021.01-rc5

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-05 16:20:26 -05:00
..
doc armv8: lx2162a: Add Soc changes to support LX2162A 2020-12-10 13:56:39 +05:30
cpu.c armv8: lx2162a: Add Soc changes to support LX2162A 2020-12-10 13:56:39 +05:30
cpu.h SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
fdt.c Prepare v2021.01-rc5 2021-01-05 16:20:26 -05:00
fsl_lsch2_serdes.c common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
fsl_lsch2_speed.c common: Move clock functions into a new file 2020-01-17 13:27:29 -05:00
fsl_lsch3_serdes.c armv8: lx2162a: Add Soc changes to support LX2162A 2020-12-10 13:56:39 +05:30
fsl_lsch3_speed.c armv8: lx2162a: Add Soc changes to support LX2162A 2020-12-10 13:56:39 +05:30
icid.c armv8: fsl-layerscape: make icid setup endianness aware 2019-08-22 09:07:36 +05:30
Kconfig armv8: lx2162a: Add Soc changes to support LX2162A 2020-12-10 13:56:39 +05:30
lowlevel.S armv8: layerscape: don't initialize GIC in SPL 2020-12-04 16:09:06 -05:00
ls1012a_serdes.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
ls1028_ids.c common: Drop log.h from common header 2020-05-18 21:19:18 -04:00
ls1028a_serdes.c armv8: ls1028a_serdes: Add few missing serdes protocols 2020-01-24 14:28:26 +05:30
ls1043_ids.c armv8: fsl-layerscape: fix SEC QI ICID setup 2019-03-03 22:01:09 +05:30
ls1043a_psci.S SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
ls1043a_serdes.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
ls1046_ids.c armv8: fsl-layerscape: fix SEC QI ICID setup 2019-03-03 22:01:09 +05:30
ls1046a_serdes.c armv8: ls1046afrwy: Add support for LS1046AFRWY platform 2019-06-19 12:54:57 +05:30
ls1088_ids.c armv8: fsl-layerscape: guard caam specific defines 2019-11-08 11:13:38 +05:30
ls1088a_serdes.c armv8: fsl-layerscape: LS1044A/1048A: enable Only 1x 10GE port 2020-01-24 14:28:26 +05:30
ls2080a_serdes.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
ls2088_ids.c armv8: ls2088a: add icid setup for platform devices 2019-11-08 11:13:38 +05:30
lx2160_ids.c armv8: lx2160a: add icid setup for platform devices 2019-11-08 11:13:38 +05:30
lx2160a_serdes.c armv8: lx2162a: Add Soc changes to support LX2162A 2020-12-10 13:56:39 +05:30
Makefile armv8: lx2162a: Add Soc changes to support LX2162A 2020-12-10 13:56:39 +05:30
mp.c armv8: layerscape: relocate spin table if EFI_LOADER is enabled 2020-07-27 14:16:28 +05:30
ppa.c treewide: use CONFIG_IS_ENABLED() for ARMV8_SEC_FIRMWARE_SUPPORT 2020-12-04 16:09:05 -05:00
soc.c armv8: fsl-layerscape: Fix automatic setting of bootmcd with TF-A 2020-12-10 13:56:39 +05:30
spintable.S armv8: layerscape: rework spin table 2020-07-27 14:16:28 +05:30
spl.c common: Drop log.h from common header 2020-05-18 21:19:18 -04:00