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https://github.com/u-boot/u-boot.git
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
488 lines
16 KiB
C
488 lines
16 KiB
C
/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
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* U-Boot port on STx XTc 8xx board
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* Mostly copied from Panto's NETTA2 board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC875 1 /* This is a MPC875 CPU */
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#define CONFIG_STXXTC 1 /* ...on a STx XTc board */
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#define CONFIG_SYS_TEXT_BASE 0x40F00000
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 115200 /* console baudrate = 115.2kbps */
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#define CONFIG_XIN 10000000 /* 10 MHz input xtal */
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/* Select one of few clock rates defined later in this file.
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*/
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/* #define MPC8XX_HZ 50000000 */
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#define MPC8XX_HZ 66666666
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#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"tftpboot; " \
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"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
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"bootm"
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#define CONFIG_SOURCE
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#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_STATUS_LED 1 /* Status LED enabled */
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#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_NISDOMAIN
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#undef CONFIG_MAC_PARTITION
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#undef CONFIG_DOS_PARTITION
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#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
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#define FEC_ENET 1 /* eth.c needs it that way... */
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#undef CONFIG_SYS_DISCOVER_PHY
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#define CONFIG_MII 1
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#define CONFIG_MII_INIT 1
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#undef CONFIG_RMII
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#define CONFIG_ETHER_ON_FEC1 1
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#define CONFIG_FEC1_PHY 1 /* phy address of FEC */
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#undef CONFIG_FEC1_PHY_NORXERR
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#define CONFIG_ETHER_ON_FEC2 1
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#define CONFIG_FEC2_PHY 3
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#undef CONFIG_FEC2_PHY_NORXERR
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#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PING
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#define CONFIG_BOARD_EARLY_INIT_F 1
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#define CONFIG_MISC_INIT_R
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "xtc> " /* Monitor Command Prompt */
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#define CONFIG_SYS_HUSH_PARSER 1
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CONFIG_SYS_IMMR 0xFF000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0x40000000
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#if defined(DEBUG)
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#else
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#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#endif
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/* yes this is weird, I know :) */
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE | 0x00F00000)
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CONFIG_SYS_RESET_ADDRESS 0x80000000
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
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#define CONFIG_ENV_OFFSET 0
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#define CONFIG_ENV_SIZE 0x4000
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x00010000)
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#define CONFIG_ENV_OFFSET_REDUND 0
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_FLASH_CFI_DRIVER 1
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#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x2000000 }
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#define CONFIG_SYS_FLASH_PROTECTION
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register 11-27
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit
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*
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*/
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#if CONFIG_XIN == 10000000
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#if MPC8XX_HZ == 50000000
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#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
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(1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
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PLPRCR_TEXPS)
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#elif MPC8XX_HZ == 66666666
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#define CONFIG_SYS_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
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(1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
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PLPRCR_TEXPS)
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#else
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#error unsupported CPU freq for XIN = 10MHz
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#endif
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#else
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#error unsupported freq for XIN (must be 10MHz)
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#endif
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/*
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*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*
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* Note: When TBS == 0 the timebase is independent of current cpu clock.
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*/
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#define SCCR_MASK SCCR_EBDF11
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#if MPC8XX_HZ > 66666666
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#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00 | SCCR_EBDF01)
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#else
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#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00)
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#endif
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
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/*#define CONFIG_SYS_DER 0x2002000F*/
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#define CONFIG_SYS_DER 0
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
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#define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */
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/* used to re-map FLASH both when starting from SRAM or FLASH:
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* restrict access enough to keep SRAM working (if any)
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* but not too much to meddle with FLASH accesses
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*/
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#define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */
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#define CONFIG_SYS_REMAP_OR_AM 0x80000000
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#define CONFIG_SYS_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
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/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
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#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
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#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
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#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
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#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
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#define CONFIG_SYS_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_FLASH)
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#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
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/*
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* BR4 and OR4 (SDRAM)
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*
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*/
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#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
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#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
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/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
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#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
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#define CONFIG_SYS_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
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#define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
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/*
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* Memory Periodic Timer Prescaler
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*/
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/*
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* Memory Periodic Timer Prescaler
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*
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* The Divider for PTA (refresh timer) configuration is based on an
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* example SDRAM configuration (64 MBit, one bank). The adjustment to
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* the number of chip selects (NCS) and the actually needed refresh
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* rate is done by setting MPTPR.
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*
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* PTA is calculated from
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* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
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*
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* gclk CPU clock (not bus clock!)
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* Trefresh Refresh cycle * 4 (four word bursts used)
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*
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* 4096 Rows from SDRAM example configuration
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* 1000 factor s -> ms
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* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
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* 4 Number of refresh cycles per period
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* 64 Refresh cycle in ms per number of rows
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* --------------------------------------------
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* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
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*
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* 50 MHz => 50.000.000 / Divider = 98
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* 66 Mhz => 66.000.000 / Divider = 129
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* 80 Mhz => 80.000.000 / Divider = 156
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*/
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#define CONFIG_SYS_MAMR_PTA 234
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/*
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* For 16 MBit, refresh rates could be 31.3 us
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* (= 64 ms / 2K = 125 / quad bursts).
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* For a simpler initialization, 15.6 us is used instead.
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*
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* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
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* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
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*/
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#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
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#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
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/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
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#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
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#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
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/*
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* MAMR settings for SDRAM
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*/
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/* 8 column SDRAM */
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#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
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MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
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/* 9 column SDRAM */
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#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
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MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
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#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
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/****************************************************************/
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#define NAND_SIZE 0x00010000 /* 64K */
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#define NAND_BASE 0xF1000000
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/*****************************************************************************/
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#define CONFIG_SYS_DIRECT_FLASH_TFTP
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/*****************************************************************************/
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/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB,
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* CxOE and CxRESET. We use the CxOE.
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*/
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#define STATUS_LED_BIT 0x00000080 /* bit 24 */
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#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
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#define STATUS_LED_STATE STATUS_LED_BLINKING
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#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
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#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
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#ifndef __ASSEMBLY__
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/* LEDs */
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/* led_id_t is unsigned int mask */
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typedef unsigned int led_id_t;
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#define __led_toggle(_msk) \
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do { \
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((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
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} while(0)
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#define __led_set(_msk, _st) \
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do { \
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if ((_st)) \
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((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
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else \
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((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
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} while(0)
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#define __led_init(msk, st) __led_set(msk, st)
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#endif
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/******************************************************************************/
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
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#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
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#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
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|
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/******************************************************************************/
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|
|
|
/* use board specific hardware */
|
|
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
|
#define CONFIG_HW_WATCHDOG
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|
|
/*****************************************************************************/
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|
|
#define CONFIG_AUTO_COMPLETE 1
|
|
#define CONFIG_CRC32_VERIFY 1
|
|
#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
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|
|
|
/*****************************************************************************/
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|
|
|
/* pass open firmware flattened device tree */
|
|
#define CONFIG_OF_LIBFDT 1
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|
|
|
#define OF_TBCLK (MPC8XX_HZ / 16)
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|
|
#endif /* __CONFIG_H */
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