mirror of
https://github.com/u-boot/u-boot.git
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c2120fbfbc
The sandburst-specific i2c drivers have been deleted, conflict was just over the SPDX conversion. Conflicts: board/sandburst/common/ppc440gx_i2c.c board/sandburst/common/ppc440gx_i2c.h Signed-off-by: Tom Rini <trini@ti.com>
447 lines
14 KiB
C
447 lines
14 KiB
C
/*
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* (C) Copyright 2001, 2002
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* Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* ------------------------------------------------------------------------- */
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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/* Environments */
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/* bootargs */
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#define CONFIG_BOOTARGS \
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"console=ttyS0,9600 init=/linuxrc " \
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"root=/dev/nfs rw nfsroot=192.168.0.1:" \
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"/tftpboot/target " \
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"ip=192.168.0.2:192.168.0.1:192.168.0.1:" \
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"255.255.255.0:debris:eth0:none " \
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"mtdparts=phys:12m(root),-(kernel)"
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/* bootcmd */
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#define CONFIG_BOOTCOMMAND \
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"tftp 800000 pImage; " \
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"setenv bootargs console=ttyS0,9600 init=/linuxrc " \
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"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:" \
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"${netmask}:${hostname}:eth0:none " \
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"mtdparts=phys:12m(root),-(kernel); " \
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"bootm 800000"
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/* bootdelay */
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#define CONFIG_BOOTDELAY 5 /* autoboot 5s */
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/* baudrate */
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#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
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/* loads_echo */
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#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
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/* ethaddr */
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#undef CONFIG_ETHADDR
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/* eth2addr */
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#undef CONFIG_ETH2ADDR
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/* eth3addr */
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#undef CONFIG_ETH3ADDR
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/* ipaddr */
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#define CONFIG_IPADDR 192.168.0.2
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/* serverip */
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#define CONFIG_SERVERIP 192.168.0.1
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/* autoload */
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#undef CONFIG_SYS_AUTOLOAD
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/* rootpath */
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#define CONFIG_ROOTPATH "/tftpboot/target"
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/* gatewayip */
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#define CONFIG_GATEWAYIP 192.168.0.1
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/* netmask */
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#define CONFIG_NETMASK 255.255.255.0
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/* hostname */
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#define CONFIG_HOSTNAME debris
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/* bootfile */
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#define CONFIG_BOOTFILE "pImage"
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/* loadaddr */
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#define CONFIG_LOADADDR 800000
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/* preboot */
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#undef CONFIG_PREBOOT
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/* clocks_in_mhz */
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#undef CONFIG_CLOCKS_IN_MHZ
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC824X 1
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#define CONFIG_MPC8245 1
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#define CONFIG_DEBRIS 1
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#if 0
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#define USE_DINK32 1
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#else
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#undef USE_DINK32
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#endif
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_DRAM_SPEED 100 /* MHz */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_KGDB
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SAVES
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#define CONFIG_CMD_SDRAM
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#define CONFIG_PCI_PNP
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#define CONFIG_EEPRO100
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#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define CONFIG_EEPRO100_SROM_WRITE
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#define PCI_ENET0_IOADDR 0x80000000
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#define PCI_ENET0_MEMADDR 0x80000000
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#define PCI_ENET1_IOADDR 0x81000000
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#define PCI_ENET1_MEMADDR 0x81000000
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
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#if defined (USE_DINK32)
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#define CONFIG_SYS_MONITOR_LEN 0x00040000
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#define CONFIG_SYS_MONITOR_BASE 0x00090000
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#define CONFIG_SYS_RAMBOOT 1
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#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#else
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#undef CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_MONITOR_LEN 0x00040000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#endif
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#define CONFIG_SYS_FLASH_BASE 0x7C000000
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#define CONFIG_SYS_FLASH_SIZE (16*1024*1024) /* debris has tiny eeprom */
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#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
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#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
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#define CONFIG_SYS_EUMB_ADDR 0xFC000000
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#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
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#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000
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#define FLASH_BASE0_PRELIM 0x7C000000 /* debris flash */
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/*
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* JFFS2 partitions
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*
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*/
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/* No command line, one static partition, whole device */
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#undef CONFIG_CMD_MTDPARTS
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#define CONFIG_JFFS2_DEV "nor0"
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#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
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#define CONFIG_JFFS2_PART_OFFSET 0x00000000
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/* mtdparts command line support */
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/* Use first bank for JFFS2, second bank contains U-Boot.
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*
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* Note: fake mtd_id's used, no linux mtd map file.
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*/
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/*
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#define CONFIG_CMD_MTDPARTS
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#define MTDIDS_DEFAULT "nor0=debris-0"
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#define MTDPARTS_DEFAULT "mtdparts=debris-0:-(jffs2)"
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*/
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#define CONFIG_ENV_IS_IN_NVRAM 1
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
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#define CONFIG_ENV_ADDR 0xFF000000 /* right at the start of NVRAM */
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#define CONFIG_ENV_SIZE 0x400 /* Size of the Environment - 8K */
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#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
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#define CONFIG_SYS_NVRAM_BASE_ADDR 0xff000000
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/*
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* CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS =
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* NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
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*/
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#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900
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/*
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* select i2c support configuration
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*
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* Supported configurations are {none, software, hardware} drivers.
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* If the software driver is chosen, there are some additional
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* configuration items that the driver uses to drive the port pins.
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*/
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#define CONFIG_HARD_I2C 1 /* To enable I2C support */
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#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#ifdef CONFIG_SYS_I2C_SOFT
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#error "Soft I2C is not configured properly. Please review!"
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_SOFT_SPEED 50000
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#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
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#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
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#define I2C_ACTIVE (iop->pdir |= 0x00010000)
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#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
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#define I2C_READ ((iop->pdat & 0x00010000) != 0)
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#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
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else iop->pdat &= ~0x00010000
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#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
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else iop->pdat &= ~0x00020000
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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#endif /* CONFIG_SYS_I2C_SOFT */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM }
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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/*
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* NS16550 Configuration
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*/
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK 7372800
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#define CONFIG_SYS_NS16550_COM1 0xFF080000
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_NS16550_COM1 + 8)
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#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_NS16550_COM1 + 16)
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#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_NS16550_COM1 + 24)
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
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#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
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#define CONFIG_SYS_DLL_EXTEND 0x00
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#define CONFIG_SYS_PCI_HOLD_DEL 0x20
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#define CONFIG_SYS_ROMNAL 15 /* rom/flash next access time */
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#define CONFIG_SYS_ROMFAL 31 /* rom/flash access time */
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#define CONFIG_SYS_REFINT 430 /* # of clocks between CBR refresh cycles */
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#define CONFIG_SYS_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
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/* the following are for SDRAM only*/
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#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
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#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
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#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
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#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
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#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
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#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
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#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
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#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
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#if 0
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#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
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#endif
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#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
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#define CONFIG_SYS_EXTROM 1
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#define CONFIG_SYS_REGDIMM 0
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/* memory bank settings*/
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/*
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* only bits 20-29 are actually used from these vales to set the
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* start/end address the upper two bits will be 0, and the lower 20
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* bits will be set to 0x00000 for a start address, or 0xfffff for an
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* end address
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*/
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#define CONFIG_SYS_BANK0_START 0x00000000
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#define CONFIG_SYS_BANK0_END (0x4000000 - 1)
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#define CONFIG_SYS_BANK0_ENABLE 1
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#define CONFIG_SYS_BANK1_START 0x04000000
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#define CONFIG_SYS_BANK1_END (0x8000000 - 1)
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#define CONFIG_SYS_BANK1_ENABLE 1
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#define CONFIG_SYS_BANK2_START 0x3ff00000
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#define CONFIG_SYS_BANK2_END 0x3fffffff
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#define CONFIG_SYS_BANK2_ENABLE 0
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#define CONFIG_SYS_BANK3_START 0x3ff00000
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#define CONFIG_SYS_BANK3_END 0x3fffffff
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#define CONFIG_SYS_BANK3_ENABLE 0
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#define CONFIG_SYS_BANK4_START 0x00000000
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#define CONFIG_SYS_BANK4_END 0x00000000
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#define CONFIG_SYS_BANK4_ENABLE 0
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#define CONFIG_SYS_BANK5_START 0x00000000
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#define CONFIG_SYS_BANK5_END 0x00000000
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#define CONFIG_SYS_BANK5_ENABLE 0
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#define CONFIG_SYS_BANK6_START 0x00000000
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#define CONFIG_SYS_BANK6_END 0x00000000
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#define CONFIG_SYS_BANK6_ENABLE 0
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#define CONFIG_SYS_BANK7_START 0x00000000
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#define CONFIG_SYS_BANK7_END 0x00000000
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#define CONFIG_SYS_BANK7_ENABLE 0
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/*
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* Memory bank enable bitmask, specifying which of the banks defined above
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are actually present. MSB is for bank #7, LSB is for bank #0.
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*/
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#define CONFIG_SYS_BANK_ENABLE 0x01
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#define CONFIG_SYS_ODCR 0x75 /* configures line driver impedances, */
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/* see 8240 book for bit definitions */
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#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
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/* currently accessed page in memory */
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/* see 8240 book for details */
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/* SDRAM 0 - 256MB */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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/* stack in DCACHE @ 1GB (no backing mem) */
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#if defined(USE_DINK32)
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#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
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#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
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#else
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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#endif
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/* PCI memory */
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#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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/* Flash, config addrs, etc */
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#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/* values according to the manual */
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#define CONFIG_DRAM_50MHZ 1
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#define CONFIG_SDRAM_50MHZ
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#define CONFIG_DISK_SPINUP_TIME 1000000
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#endif /* __CONFIG_H */
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