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149 lines
3.3 KiB
C
149 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Watchdog driver for SP805 on some Layerscape SoC
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*
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* Copyright 2019 NXP
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*/
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#include <log.h>
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#include <asm/io.h>
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#include <common.h>
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#include <clk.h>
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#include <dm/device.h>
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#include <dm/fdtaddr.h>
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#include <dm/read.h>
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#include <linux/bitops.h>
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#include <watchdog.h>
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#include <wdt.h>
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#include <linux/err.h>
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#define WDTLOAD 0x000
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#define WDTCONTROL 0x008
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#define WDTINTCLR 0x00C
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#define WDTLOCK 0xC00
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#define TIME_OUT_MIN_MSECS 1
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#define TIME_OUT_MAX_MSECS 120000
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#define SYS_FSL_WDT_CLK_DIV 16
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#define INT_ENABLE BIT(0)
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#define RESET_ENABLE BIT(1)
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#define DISABLE 0
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#define UNLOCK 0x1ACCE551
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#define LOCK 0x00000001
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#define INT_MASK BIT(0)
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DECLARE_GLOBAL_DATA_PTR;
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struct sp805_wdt_priv {
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void __iomem *reg;
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unsigned long clk_rate;
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};
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static int sp805_wdt_reset(struct udevice *dev)
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{
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struct sp805_wdt_priv *priv = dev_get_priv(dev);
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writel(UNLOCK, priv->reg + WDTLOCK);
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writel(INT_MASK, priv->reg + WDTINTCLR);
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writel(LOCK, priv->reg + WDTLOCK);
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readl(priv->reg + WDTLOCK);
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return 0;
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}
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static int sp805_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
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{
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u32 load_value;
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u32 load_time;
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struct sp805_wdt_priv *priv = dev_get_priv(dev);
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load_time = (u32)timeout;
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if (timeout < TIME_OUT_MIN_MSECS)
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load_time = TIME_OUT_MIN_MSECS;
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else if (timeout > TIME_OUT_MAX_MSECS)
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load_time = TIME_OUT_MAX_MSECS;
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/* sp805 runs counter with given value twice, so when the max timeout is
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* set 120s, the gd->bus_clk is less than 1145MHz, the load_value will
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* not overflow.
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*/
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if (gd->bus_clk) {
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load_value = (gd->bus_clk) /
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(2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
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} else {
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/* platform provide clk */
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load_value = (timeout / 2) * (priv->clk_rate / 1000);
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}
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writel(UNLOCK, priv->reg + WDTLOCK);
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writel(load_value, priv->reg + WDTLOAD);
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writel(INT_MASK, priv->reg + WDTINTCLR);
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writel(INT_ENABLE | RESET_ENABLE, priv->reg + WDTCONTROL);
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writel(LOCK, priv->reg + WDTLOCK);
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readl(priv->reg + WDTLOCK);
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return 0;
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}
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static int sp805_wdt_stop(struct udevice *dev)
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{
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struct sp805_wdt_priv *priv = dev_get_priv(dev);
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writel(UNLOCK, priv->reg + WDTLOCK);
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writel(DISABLE, priv->reg + WDTCONTROL);
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writel(LOCK, priv->reg + WDTLOCK);
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readl(priv->reg + WDTLOCK);
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return 0;
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}
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static int sp805_wdt_expire_now(struct udevice *dev, ulong flags)
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{
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sp805_wdt_start(dev, 0, flags);
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return 0;
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}
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static int sp805_wdt_probe(struct udevice *dev)
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{
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debug("%s: Probing wdt%u (sp805-wdt)\n", __func__, dev->seq);
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return 0;
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}
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static int sp805_wdt_ofdata_to_platdata(struct udevice *dev)
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{
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struct sp805_wdt_priv *priv = dev_get_priv(dev);
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struct clk clk;
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priv->reg = (void __iomem *)dev_read_addr(dev);
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if (IS_ERR(priv->reg))
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return PTR_ERR(priv->reg);
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if (!clk_get_by_index(dev, 0, &clk))
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priv->clk_rate = clk_get_rate(&clk);
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return 0;
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}
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static const struct wdt_ops sp805_wdt_ops = {
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.start = sp805_wdt_start,
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.reset = sp805_wdt_reset,
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.stop = sp805_wdt_stop,
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.expire_now = sp805_wdt_expire_now,
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};
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static const struct udevice_id sp805_wdt_ids[] = {
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{ .compatible = "arm,sp805-wdt" },
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{}
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};
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U_BOOT_DRIVER(sp805_wdt) = {
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.name = "sp805_wdt",
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.id = UCLASS_WDT,
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.of_match = sp805_wdt_ids,
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.probe = sp805_wdt_probe,
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.priv_auto_alloc_size = sizeof(struct sp805_wdt_priv),
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.ofdata_to_platdata = sp805_wdt_ofdata_to_platdata,
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.ops = &sp805_wdt_ops,
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};
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