mirror of
https://github.com/u-boot/u-boot.git
synced 2024-12-14 07:13:28 +08:00
a09fea1d28
- In ARMv8 NXP Layerscape platforms we also need to make use of CONFIG_SYS_RELOC_GD_ENV_ADDR now, do so. - On ENV_IS_IN_REMOTE, CONFIG_ENV_OFFSET is never used, drop the define to 0. - Add Kconfig entry for ENV_ADDR. - Make ENV_ADDR / ENV_OFFSET depend on the env locations that use it. - Add ENV_xxx_REDUND options that depend on their primary option and SYS_REDUNDAND_ENVIRONMENT - On a number of PowerPC platforms, use SPL_ENV_ADDR not CONFIG_ENV_ADDR for the pre-main-U-Boot environment location. - On ENV_IS_IN_SPI_FLASH, check not for CONFIG_ENV_ADDR being set but rather it being non-zero, as it will now be zero by default. - Rework the env_offset absolute in env/embedded.o to not use CONFIG_ENV_OFFSET as it was the only use of ENV_OFFSET within ENV_IS_IN_FLASH. - Migrate all platforms. Cc: Wolfgang Denk <wd@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
462 lines
14 KiB
C
462 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2014
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
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*
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 family */
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#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
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/*
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* SERDES
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*/
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#define CONFIG_FSL_SERDES
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#define CONFIG_FSL_SERDES1 0xe3000
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
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| DDRCDR_PZ_LOZ \
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| DDRCDR_NZ_LOZ \
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| DDRCDR_ODT \
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| DDRCDR_Q_DRN)
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/* 0x7b880001 */
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/*
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* Manually set up DDR parameters
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* consist of one chip NT5TU64M16HG from NANYA
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*/
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#define CONFIG_SYS_DDR_SIZE 128 /* MB */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
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| CSCONFIG_ODT_RD_NEVER \
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| CSCONFIG_ODT_WR_ONLY_CURRENT \
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| CSCONFIG_BANK_BIT_3 \
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| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
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/* 0x80010102 */
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#define CONFIG_SYS_DDR_TIMING_3 0
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#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
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| (0 << TIMING_CFG0_WRT_SHIFT) \
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| (0 << TIMING_CFG0_RRT_SHIFT) \
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| (0 << TIMING_CFG0_WWT_SHIFT) \
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| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
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| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
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| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
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/* 0x00260802 */
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#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
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| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
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| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
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| (7 << TIMING_CFG1_CASLAT_SHIFT) \
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| (9 << TIMING_CFG1_REFREC_SHIFT) \
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| (2 << TIMING_CFG1_WRREC_SHIFT) \
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| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
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| (2 << TIMING_CFG1_WRTORD_SHIFT))
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/* 0x26279222 */
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#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
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| (4 << TIMING_CFG2_CPO_SHIFT) \
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| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
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| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
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| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
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| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
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| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
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/* 0x021848c5 */
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#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
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| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
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/* 0x08240100 */
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#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
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| SDRAM_CFG_SDRAM_TYPE_DDR2 \
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| SDRAM_CFG_DBW_16)
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/* 0x43100000 */
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
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#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
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| (0x0242 << SDRAM_MODE_SD_SHIFT))
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/* ODT 150ohm CL=4, AL=0 on SDRAM */
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#define CONFIG_SYS_DDR_MODE2 0x00000000
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/*
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* Memory test
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*/
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#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x07f00000
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/*
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* The reserved memory
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
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/*
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* Initial RAM Base Address Setup
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*/
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_FLASH_CFI_LEGACY
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#define CONFIG_SYS_FLASH_LEGACY_512Kx16
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#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
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#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 135
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_FPGA_DONE(k) 0x0010
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#define CONFIG_SYS_FPGA_COUNT 1
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#define CONFIG_SYS_MCLINK_MAX 3
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#define CONFIG_SYS_FPGA_PTR \
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{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
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#define CONFIG_SYS_FPGA_NO_RFL_HI
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/*
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* Serial Port
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
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/* Pass open firmware flat tree */
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_PCA953X /* NXP PCA9554 */
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#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
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{0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
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#define CONFIG_PCA9698 /* NXP PCA9698 */
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#define CONFIG_SYS_I2C_IHS
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#define CONFIG_SYS_I2C_IHS_CH0
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#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
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#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
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#define CONFIG_SYS_I2C_IHS_CH1
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#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
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#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
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#define CONFIG_SYS_I2C_IHS_CH2
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#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
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#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
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#define CONFIG_SYS_I2C_IHS_CH3
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#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
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#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
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#ifdef CONFIG_STRIDER_CON_DP
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#define CONFIG_SYS_I2C_IHS_DUAL
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#define CONFIG_SYS_I2C_IHS_CH0_1
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#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
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#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
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#define CONFIG_SYS_I2C_IHS_CH1_1
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#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
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#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
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#define CONFIG_SYS_I2C_IHS_CH2_1
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#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
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#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
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#define CONFIG_SYS_I2C_IHS_CH3_1
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#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
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#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
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#endif
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define CONFIG_SYS_I2C_SOFT
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#define CONFIG_SOFT_I2C_READ_REPEATED_START
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#define CONFIG_SYS_I2C_SOFT_SPEED 50000
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#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
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#define I2C_SOFT_DECLARATIONS2
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#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
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#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
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#define I2C_SOFT_DECLARATIONS3
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#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
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#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
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#define I2C_SOFT_DECLARATIONS4
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#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
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#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
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#if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
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#define I2C_SOFT_DECLARATIONS5
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#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
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#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
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#define I2C_SOFT_DECLARATIONS6
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#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
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#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
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#define I2C_SOFT_DECLARATIONS7
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#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
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#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
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#define I2C_SOFT_DECLARATIONS8
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#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
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#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
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#endif
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#ifdef CONFIG_STRIDER_CON_DP
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#define I2C_SOFT_DECLARATIONS9
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#define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
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#define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
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#define I2C_SOFT_DECLARATIONS10
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#define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
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#define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
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#define I2C_SOFT_DECLARATIONS11
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#define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
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#define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
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#define I2C_SOFT_DECLARATIONS12
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#define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
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#define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
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#endif
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#ifdef CONFIG_STRIDER_CON
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#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
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#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
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#define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8}
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#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
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#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
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{12, 0x4c} }
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#elif defined(CONFIG_STRIDER_CON_DP)
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#define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
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#define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7}
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#define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7}
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#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
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#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
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{12, 0x4c} }
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#elif defined(CONFIG_STRIDER_CPU_DP)
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#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
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#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
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#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
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#define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \
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{8, 0x4c} }
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#else
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#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
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#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
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#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
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#define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
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{4, 0x18} }
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#endif
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#ifndef __ASSEMBLY__
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void fpga_gpio_set(unsigned int bus, int pin);
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void fpga_gpio_clear(unsigned int bus, int pin);
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int fpga_gpio_get(unsigned int bus, int pin);
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void fpga_control_set(unsigned int bus, int pin);
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void fpga_control_clear(unsigned int bus, int pin);
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#endif
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#ifdef CONFIG_STRIDER_CON
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#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
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#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
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#define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
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(I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
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#elif defined(CONFIG_STRIDER_CON_DP)
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#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
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#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
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#define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
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#else
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#define I2C_SDA_GPIO 0x0040
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#define I2C_SCL_GPIO 0x0020
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#define I2C_FPGA_IDX I2C_ADAP_HWNR
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#endif
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#ifdef CONFIG_STRIDER_CON_DP
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#define I2C_ACTIVE \
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do { \
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if (I2C_ADAP_HWNR > 7) \
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fpga_control_set(I2C_FPGA_IDX, 0x0004); \
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else \
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fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
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} while (0)
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#else
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#define I2C_ACTIVE { }
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#endif
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#define I2C_TRISTATE { }
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#define I2C_READ \
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(fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
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#define I2C_SDA(bit) \
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do { \
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if (bit) \
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fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
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else \
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fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
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} while (0)
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#define I2C_SCL(bit) \
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do { \
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if (bit) \
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fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
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else \
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fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
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} while (0)
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#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
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/*
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* Software (bit-bang) MII driver configuration
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*/
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#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
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#define CONFIG_BITBANGMII_MULTI
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/*
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* OSD Setup
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*/
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#define CONFIG_SYS_OSD_SCREENS 1
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#define CONFIG_SYS_DP501_DIFFERENTIAL
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#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
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#ifdef CONFIG_STRIDER_CON_DP
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#define CONFIG_SYS_OSD_DH
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#endif
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CONFIG_SYS_PCIE1_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
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#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
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#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
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/* enable PCIE clock */
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#define CONFIG_SYS_SCCR_PCIEXP1CM 1
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#define CONFIG_PCI_INDIRECT_BRIDGE
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#define CONFIG_PCIE
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
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/*
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* TSEC
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*/
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
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/*
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* TSEC ethernet configuration
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*/
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#define CONFIG_TSEC1
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#define CONFIG_TSEC1_NAME "eTSEC0"
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#define TSEC1_PHY_ADDR 1
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#define TSEC1_PHYIDX 0
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#define TSEC1_FLAGS 0
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|
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/* Options are: eTSEC[0-1] */
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#define CONFIG_ETHPRIME "eTSEC0"
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|
|
|
/*
|
|
* Environment
|
|
*/
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|
|
|
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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|
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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|
|
|
/*
|
|
* Command line configuration.
|
|
*/
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|
|
|
/*
|
|
* Miscellaneous configurable options
|
|
*/
|
|
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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|
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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|
|
|
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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|
|
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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|
|
|
/*
|
|
* For booting Linux, the board info and command line data
|
|
* have to be in the first 256 MB of memory, since this is
|
|
* the maximum mapped by the Linux kernel during initialization.
|
|
*/
|
|
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
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|
|
|
/*
|
|
* Environment Configuration
|
|
*/
|
|
|
|
#define CONFIG_ENV_OVERWRITE
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|
|
|
#if defined(CONFIG_TSEC_ENET)
|
|
#define CONFIG_HAS_ETH0
|
|
#endif
|
|
|
|
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
|
|
|
|
|
|
#define CONFIG_HOSTNAME "hrcon"
|
|
#define CONFIG_ROOTPATH "/opt/nfsroot"
|
|
#define CONFIG_BOOTFILE "uImage"
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"netdev=eth0\0" \
|
|
"consoledev=ttyS1\0" \
|
|
"u-boot=u-boot.bin\0" \
|
|
"kernel_addr=1000000\0" \
|
|
"fdt_addr=C00000\0" \
|
|
"fdtfile=hrcon.dtb\0" \
|
|
"load=tftp ${loadaddr} ${u-boot}\0" \
|
|
"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
|
|
" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
|
|
" +${filesize};cp.b ${fileaddr} " \
|
|
__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
|
|
"upd=run load update\0" \
|
|
|
|
#define CONFIG_NFSBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/nfs rw " \
|
|
"nfsroot=$serverip:$rootpath " \
|
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"tftp ${kernel_addr} $bootfile;" \
|
|
"tftp ${fdt_addr} $fdtfile;" \
|
|
"bootm ${kernel_addr} - ${fdt_addr}"
|
|
|
|
#define CONFIG_MMCBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
|
|
"ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
|
|
"bootm ${kernel_addr} - ${fdt_addr}"
|
|
|
|
#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
|
|
|
|
#endif /* __CONFIG_H */
|