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6d0bdfdde5
common/dlmalloc.c is quite big, both in .text and .data usage. E.g. for a Mele_M9 sun6i board build this reduces .text from 0x4214 to 0x3b94 bytes, and .data from 0x54c to 0x144 bytes. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Tom Rini <trini@konsulko.com>
267 lines
7.7 KiB
C
267 lines
7.7 KiB
C
/*
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* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
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*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* Some init for sunxi platform.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mmc.h>
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#include <i2c.h>
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#include <serial.h>
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#ifdef CONFIG_SPL_BUILD
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#include <spl.h>
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#endif
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/spl.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/timer.h>
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#include <asm/arch/tzpc.h>
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#include <asm/arch/mmc.h>
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#include <linux/compiler.h>
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struct fel_stash {
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uint32_t sp;
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uint32_t lr;
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uint32_t cpsr;
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uint32_t sctlr;
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uint32_t vbar;
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uint32_t cr;
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};
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struct fel_stash fel_stash __attribute__((section(".data")));
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static int gpio_init(void)
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{
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#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
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#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
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/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
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sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
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#endif
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#if defined(CONFIG_MACH_SUN8I)
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sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
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#else
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sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
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#endif
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sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
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#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
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sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
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sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
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sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
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sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
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sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
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sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
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sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
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sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
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sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
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sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
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sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
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sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
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sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
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#else
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#error Unsupported console port number. Please fix pin mux settings in board.c
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#endif
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return 0;
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}
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void spl_board_load_image(void)
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{
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debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
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return_to_fel(fel_stash.sp, fel_stash.lr);
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}
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void s_init(void)
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{
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#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
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/* Magic (undocmented) value taken from boot0, without this DRAM
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* access gets messed up (seems cache related) */
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setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
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#endif
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#if defined CONFIG_MACH_SUN6I || \
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defined CONFIG_MACH_SUN7I || \
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defined CONFIG_MACH_SUN8I
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/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
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asm volatile(
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"mrc p15, 0, r0, c1, c0, 1\n"
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"orr r0, r0, #1 << 6\n"
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"mcr p15, 0, r0, c1, c0, 1\n");
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#endif
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#if defined CONFIG_MACH_SUN6I
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/* Enable non-secure access to the RTC */
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tzpc_init();
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#endif
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clock_init();
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timer_init();
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gpio_init();
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i2c_init_board();
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}
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#ifdef CONFIG_SPL_BUILD
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DECLARE_GLOBAL_DATA_PTR;
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/* The sunxi internal brom will try to loader external bootloader
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* from mmc0, nand flash, mmc2.
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*/
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u32 spl_boot_device(void)
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{
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struct mmc *mmc0, *mmc1;
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/*
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* When booting from the SD card or NAND memory, the "eGON.BT0"
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* signature is expected to be found in memory at the address 0x0004
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* (see the "mksunxiboot" tool, which generates this header).
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*
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* When booting in the FEL mode over USB, this signature is patched in
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* memory and replaced with something else by the 'fel' tool. This other
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* signature is selected in such a way, that it can't be present in a
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* valid bootable SD card image (because the BROM would refuse to
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* execute the SPL in this case).
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*
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* This checks for the signature and if it is not found returns to
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* the FEL code in the BROM to wait and receive the main u-boot
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* binary over USB. If it is found, it determines where SPL was
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* read from.
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*/
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if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
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return BOOT_DEVICE_BOARD;
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/* The BROM will try to boot from mmc0 first, so try that first. */
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mmc_initialize(gd->bd);
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mmc0 = find_mmc_device(0);
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if (sunxi_mmc_has_egon_boot_signature(mmc0))
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return BOOT_DEVICE_MMC1;
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/* Fallback to booting NAND if enabled. */
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if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT))
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return BOOT_DEVICE_NAND;
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if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) {
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mmc1 = find_mmc_device(1);
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if (sunxi_mmc_has_egon_boot_signature(mmc1)) {
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/*
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* spl_mmc.c: spl_mmc_load_image() is hard-coded to
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* use find_mmc_device(0), no matter what we
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* return. Swap mmc0 and mmc2 to make this work.
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*/
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mmc0->block_dev.dev = 1;
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mmc1->block_dev.dev = 0;
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return BOOT_DEVICE_MMC2;
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}
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}
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panic("Could not determine boot source\n");
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return -1; /* Never reached */
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}
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/* No confirmation data available in SPL yet. Hardcode bootmode */
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u32 spl_boot_mode(void)
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{
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return MMCSD_MODE_RAW;
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}
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void board_init_f(ulong dummy)
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{
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spl_init();
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preloader_console_init();
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#ifdef CONFIG_SPL_I2C_SUPPORT
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/* Needed early by sunxi_board_init if PMU is enabled */
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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#endif
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sunxi_board_init();
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}
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#endif
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void reset_cpu(ulong addr)
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{
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#ifdef CONFIG_SUNXI_GEN_SUN4I
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static const struct sunxi_wdog *wdog =
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&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
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/* Set the watchdog for its shortest interval (.5s) and wait */
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writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
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writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
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while (1) {
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/* sun5i sometimes gets stuck without this */
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writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
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}
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#endif
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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static const struct sunxi_wdog *wdog =
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((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
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/* Set the watchdog for its shortest interval (.5s) and wait */
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writel(WDT_CFG_RESET, &wdog->cfg);
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writel(WDT_MODE_EN, &wdog->mode);
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writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
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while (1) { }
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#endif
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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#ifdef CONFIG_CMD_NET
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int cpu_eth_init(bd_t *bis)
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{
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__maybe_unused int rc;
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#ifdef CONFIG_MACPWR
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gpio_request(CONFIG_MACPWR, "macpwr");
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gpio_direction_output(CONFIG_MACPWR, 1);
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mdelay(200);
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#endif
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#ifdef CONFIG_SUNXI_GMAC
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rc = sunxi_gmac_initialize(bis);
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if (rc < 0) {
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printf("sunxi: failed to initialize gmac\n");
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return rc;
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}
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#endif
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return 0;
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}
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#endif
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