u-boot/arch/riscv
Tom Rini 6d0453d889 Prepare v2021.07-rc5
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Merge tag 'v2021.07-rc5' into next

Prepare v2021.07-rc5

# gpg: Signature made Mon 28 Jun 2021 03:39:36 PM EDT
# gpg:                using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C
# gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate]

# Conflicts:
#	configs/am64x_evm_r5_defconfig
2021-06-28 16:22:13 -04:00
..
cpu riscv: cpu: fu740: clear feature disable CSR 2021-05-31 16:35:55 +08:00
dts Prepare v2021.07-rc5 2021-06-28 16:22:13 -04:00
include/asm riscv: cpu: fu740: Add support for cpu fu740 2021-05-31 16:35:53 +08:00
lib riscv: andes_plic: Fix riscv_get_ipi() mask 2021-06-17 09:39:46 +08:00
config.mk kconfig / kbuild: Re-sync with Linux 4.19 2020-04-10 11:18:32 -04:00
Kconfig board: sifive: add HiFive Unmatched board support 2021-05-31 16:35:55 +08:00
Makefile riscv: add Kconfig entries for the code model 2018-12-18 09:56:26 +08:00