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3ff02c27d5
On OMAP1610 platforms check if booting from RAM(CS0) or flash(CS3). Set flash base accordingly, and decide whether to do or skip board specific setup steps. * Patch by Josef Baumgartner, 26 May 2004: Add missing define in include/asm-m68k/global_data.h
453 lines
9.3 KiB
ArmAsm
453 lines
9.3 KiB
ArmAsm
/*
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* Board specific setup info
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*
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* (C) Copyright 2003
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* Texas Instruments, <www.ti.com>
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* Kshitij Gupta <Kshitij@ti.com>
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*
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* Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#if defined(CONFIG_OMAP1610)
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#include <./configs/omap1510.h>
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#endif
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_TEXT_BASE:
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.word TEXT_BASE /* sdram load addr from config.mk */
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.globl platformsetup
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platformsetup:
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/*------------------------------------------------------*
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*mask all IRQs by setting all bits in the INTMR default*
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*------------------------------------------------------*/
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mov r1, #0xffffffff
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ldr r0, =REG_IHL1_MIR
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str r1, [r0]
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ldr r0, =REG_IHL2_MIR
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str r1, [r0]
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/*------------------------------------------------------*
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* Set up ARM CLM registers (IDLECT1) *
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*------------------------------------------------------*/
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ldr r0, REG_ARM_IDLECT1
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ldr r1, VAL_ARM_IDLECT1
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str r1, [r0]
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/*------------------------------------------------------*
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* Set up ARM CLM registers (IDLECT2) *
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*------------------------------------------------------*/
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ldr r0, REG_ARM_IDLECT2
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ldr r1, VAL_ARM_IDLECT2
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str r1, [r0]
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/*------------------------------------------------------*
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* Set up ARM CLM registers (IDLECT3) *
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*------------------------------------------------------*/
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ldr r0, REG_ARM_IDLECT3
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ldr r1, VAL_ARM_IDLECT3
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str r1, [r0]
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#ifdef CONFIG_CS_AUTOBOOT /* do the setup depending on boot mode */
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ldr r0, CONF_STATUS
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ldr r1, [r0]
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tst r1, #0x02
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beq disable_wd /* booting from RAM, skip setup */
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#endif
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mov r1, #0x01 /* PER_EN bit */
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ldr r0, REG_ARM_RSTCT2
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strh r1, [r0] /* CLKM; Peripheral reset. */
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/* Set CLKM to Sync-Scalable */
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/* I supposedly need to enable the dsp clock before switching */
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mov r1, #0x0000
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ldr r0, REG_ARM_SYSST
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strh r1, [r0]
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mov r0, #0x400
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1:
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subs r0, r0, #0x1 /* wait for any bubbles to finish */
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bne 1b
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ldr r1, VAL_ARM_CKCTL
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ldr r0, REG_ARM_CKCTL
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strh r1, [r0]
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/* a few nops to let settle */
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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/* setup DPLL 1 */
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/* Ramp up the clock to 96Mhz */
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ldr r1, VAL_DPLL1_CTL
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ldr r0, REG_DPLL1_CTL
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strh r1, [r0]
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ands r1, r1, #0x10 /* Check if PLL is enabled. */
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beq lock_end /* Do not look for lock if BYPASS selected */
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2:
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ldrh r1, [r0]
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ands r1, r1, #0x01 /* Check the LOCK bit.*/
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beq 2b /* loop until bit goes hi. */
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lock_end:
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/*------------------------------------------------------*
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* Turn off the watchdog during init... *
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*------------------------------------------------------*/
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disable_wd:
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ldr r0, REG_WATCHDOG
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ldr r1, WATCHDOG_VAL1
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str r1, [r0]
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ldr r1, WATCHDOG_VAL2
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str r1, [r0]
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ldr r0, REG_WSPRDOG
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ldr r1, WSPRDOG_VAL1
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str r1, [r0]
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ldr r0, REG_WWPSDOG
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watch1Wait:
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ldr r1, [r0]
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tst r1, #0x10
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bne watch1Wait
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ldr r0, REG_WSPRDOG
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ldr r1, WSPRDOG_VAL2
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str r1, [r0]
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ldr r0, REG_WWPSDOG
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watch2Wait:
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ldr r1, [r0]
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tst r1, #0x10
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bne watch2Wait
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/* Set memory timings corresponding to the new clock speed */
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/* Check execution location to determine current execution location
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* and branch to appropriate initialization code.
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*/
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/* Load physical SDRAM base. */
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mov r0, #0x10000000
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/* Get current execution location. */
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mov r1, pc
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/* Compare. */
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cmp r1, r0
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/* Skip over EMIF-fast initialization if running from SDRAM. */
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bge skip_sdram
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/*
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* Delay for SDRAM initialization.
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*/
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mov r3, #0x1800 /* value should be checked */
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3:
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subs r3, r3, #0x1 /* Decrement count */
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bne 3b
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/*
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* Set SDRAM control values. Disable refresh before MRS command.
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*/
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/* mobile ddr operation */
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ldr r0, REG_SDRAM_OPERATION
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mov r2, #07
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str r2, [r0]
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/* config register */
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ldr r0, REG_SDRAM_CONFIG
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ldr r1, SDRAM_CONFIG_VAL
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str r1, [r0]
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/* manual command register */
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ldr r0, REG_SDRAM_MANUAL_CMD
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/* issue set cke high */
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mov r1, #CMD_SDRAM_CKE_SET_HIGH
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str r1, [r0]
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/* issue nop */
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mov r1, #CMD_SDRAM_NOP
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str r1, [r0]
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mov r2, #0x0100
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waitMDDR1:
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subs r2, r2, #1
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bne waitMDDR1 /* delay loop */
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/* issue precharge */
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mov r1, #CMD_SDRAM_PRECHARGE
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str r1, [r0]
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/* issue autorefresh x 2 */
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mov r1, #CMD_SDRAM_AUTOREFRESH
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str r1, [r0]
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str r1, [r0]
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/* mrs register ddr mobile */
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ldr r0, REG_SDRAM_MRS
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mov r1, #0x33
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str r1, [r0]
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/* emrs1 low-power register */
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ldr r0, REG_SDRAM_EMRS1
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/* self refresh on all banks */
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mov r1, #0
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str r1, [r0]
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ldr r0, REG_DLL_URD_CONTROL
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ldr r1, DLL_URD_CONTROL_VAL
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str r1, [r0]
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ldr r0, REG_DLL_LRD_CONTROL
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ldr r1, DLL_LRD_CONTROL_VAL
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str r1, [r0]
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ldr r0, REG_DLL_WRT_CONTROL
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ldr r1, DLL_WRT_CONTROL_VAL
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str r1, [r0]
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/* delay loop */
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mov r2, #0x0100
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waitMDDR2:
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subs r2, r2, #1
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bne waitMDDR2
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/*
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* Delay for SDRAM initialization.
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*/
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mov r3, #0x1800
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4:
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subs r3, r3, #1 /* Decrement count. */
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bne 4b
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b common_tc
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skip_sdram:
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ldr r0, REG_SDRAM_CONFIG
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ldr r1, SDRAM_CONFIG_VAL
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str r1, [r0]
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common_tc:
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/* slow interface */
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ldr r1, VAL_TC_EMIFS_CS0_CONFIG
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ldr r0, REG_TC_EMIFS_CS0_CONFIG
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str r1, [r0] /* Chip Select 0 */
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ldr r1, VAL_TC_EMIFS_CS1_CONFIG
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ldr r0, REG_TC_EMIFS_CS1_CONFIG
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str r1, [r0] /* Chip Select 1 */
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ldr r1, VAL_TC_EMIFS_CS3_CONFIG
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ldr r0, REG_TC_EMIFS_CS3_CONFIG
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str r1, [r0] /* Chip Select 3 */
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#ifdef CONFIG_H2_OMAP1610
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/* inserting additional 2 clock cycle hold time for LAN */
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ldr r0, REG_TC_EMIFS_CS1_ADVANCED
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ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
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str r1, [r0]
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#endif
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/* Start MPU Timer 1 */
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ldr r0, REG_MPU_LOAD_TIMER
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ldr r1, VAL_MPU_LOAD_TIMER
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str r1, [r0]
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ldr r0, REG_MPU_CNTL_TIMER
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ldr r1, VAL_MPU_CNTL_TIMER
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str r1, [r0]
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/* back to arch calling code */
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mov pc, lr
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/* the literal pools origin */
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.ltorg
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#ifdef CONFIG_CS_AUTOBOOT
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CONF_STATUS:
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.word 0xfffe1130 /* 32 bits */
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#endif
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REG_TC_EMIFS_CONFIG: /* 32 bits */
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.word 0xfffecc0c
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REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
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.word 0xfffecc10
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REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
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.word 0xfffecc14
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REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
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.word 0xfffecc18
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REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
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.word 0xfffecc1c
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#ifdef CONFIG_H2_OMAP1610
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REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
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.word 0xfffecc54
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#endif
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/* MPU clock/reset/power mode control registers */
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REG_ARM_CKCTL: /* 16 bits */
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.word 0xfffece00
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REG_ARM_IDLECT3: /* 16 bits */
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.word 0xfffece24
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REG_ARM_IDLECT2: /* 16 bits */
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.word 0xfffece08
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REG_ARM_IDLECT1: /* 16 bits */
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.word 0xfffece04
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REG_ARM_RSTCT2: /* 16 bits */
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.word 0xfffece14
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REG_ARM_SYSST: /* 16 bits */
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.word 0xfffece18
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/* DPLL control registers */
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REG_DPLL1_CTL: /* 16 bits */
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.word 0xfffecf00
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/* Watch Dog register */
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/* secure watchdog stop */
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REG_WSPRDOG:
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.word 0xfffeb048
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/* watchdog write pending */
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REG_WWPSDOG:
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.word 0xfffeb034
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WSPRDOG_VAL1:
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.word 0x0000aaaa
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WSPRDOG_VAL2:
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.word 0x00005555
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/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
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counter @8192 rows, 10 ns, 8 burst */
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REG_SDRAM_CONFIG:
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.word 0xfffecc20
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/* Operation register */
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REG_SDRAM_OPERATION:
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.word 0xfffecc80
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/* Manual command register */
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REG_SDRAM_MANUAL_CMD:
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.word 0xfffecc84
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/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
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REG_SDRAM_MRS:
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.word 0xfffecc70
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/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
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REG_SDRAM_EMRS1:
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.word 0xfffecc78
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/* WRT DLL register */
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REG_DLL_WRT_CONTROL:
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.word 0xfffecc68
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DLL_WRT_CONTROL_VAL:
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.word 0x03f00002
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/* URD DLL register */
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REG_DLL_URD_CONTROL:
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.word 0xfffeccc0
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DLL_URD_CONTROL_VAL:
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.word 0x00800002
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/* LRD DLL register */
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REG_DLL_LRD_CONTROL:
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.word 0xfffecccc
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REG_WATCHDOG:
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.word 0xfffec808
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REG_MPU_LOAD_TIMER:
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.word 0xfffec600
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REG_MPU_CNTL_TIMER:
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.word 0xfffec500
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/* 96 MHz Samsung Mobile DDR */
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SDRAM_CONFIG_VAL:
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.word 0x001200f4
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DLL_LRD_CONTROL_VAL:
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.word 0x00800002
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VAL_ARM_CKCTL:
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.word 0x3000
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VAL_DPLL1_CTL:
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.word 0x2830
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#ifdef CONFIG_INNOVATOROMAP1610
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VAL_TC_EMIFS_CS0_CONFIG:
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.word 0x002130b0
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VAL_TC_EMIFS_CS1_CONFIG:
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.word 0x00001131
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VAL_TC_EMIFS_CS2_CONFIG:
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.word 0x000055f0
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VAL_TC_EMIFS_CS3_CONFIG:
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.word 0x88011131
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#endif
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#ifdef CONFIG_H2_OMAP1610
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VAL_TC_EMIFS_CS0_CONFIG:
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.word 0x00203331
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VAL_TC_EMIFS_CS1_CONFIG:
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.word 0x8180fff3
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VAL_TC_EMIFS_CS2_CONFIG:
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.word 0xf800f22a
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VAL_TC_EMIFS_CS3_CONFIG:
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.word 0x88011131
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VAL_TC_EMIFS_CS1_ADVANCED:
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.word 0x00000022
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#endif
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VAL_TC_EMIFF_SDRAM_CONFIG:
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.word 0x010290fc
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VAL_TC_EMIFF_MRS:
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.word 0x00000027
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VAL_ARM_IDLECT1:
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.word 0x00000400
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VAL_ARM_IDLECT2:
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.word 0x00000886
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VAL_ARM_IDLECT3:
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.word 0x00000015
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WATCHDOG_VAL1:
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.word 0x000000f5
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WATCHDOG_VAL2:
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.word 0x000000a0
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VAL_MPU_LOAD_TIMER:
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.word 0xffffffff
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VAL_MPU_CNTL_TIMER:
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.word 0xffffffa1
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/* command values */
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.equ CMD_SDRAM_NOP, 0x00000000
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.equ CMD_SDRAM_PRECHARGE, 0x00000001
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.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
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.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007
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