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https://github.com/u-boot/u-boot.git
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cd392fe8a0
Newer Intel chips require a Management Engine which requires a particular format for the SPI flash that contains the boot loader. Add a tool that supports creating and modifying these ROM images. This tool is from Chrome OS but has been cleaned up to use U-Boot style and to add comments. A few features have been added also. Signed-off-by: Simon Glass <sjg@chromium.org>
89 lines
1.4 KiB
C
89 lines
1.4 KiB
C
/*
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* ifdtool - Manage Intel Firmware Descriptor information
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*
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* Copyright (C) 2011 The ChromiumOS Authors.
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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* From Coreboot project
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*/
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#include <stdint.h>
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#define __packed __attribute__((packed))
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#define IFDTOOL_VERSION "1.1-U-Boot"
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enum spi_frequency {
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SPI_FREQUENCY_20MHZ = 0,
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SPI_FREQUENCY_33MHZ = 1,
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SPI_FREQUENCY_50MHZ = 4,
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};
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enum component_density {
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COMPONENT_DENSITY_512KB = 0,
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COMPONENT_DENSITY_1MB = 1,
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COMPONENT_DENSITY_2MB = 2,
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COMPONENT_DENSITY_4MB = 3,
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COMPONENT_DENSITY_8MB = 4,
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COMPONENT_DENSITY_16MB = 5,
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};
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/* flash descriptor */
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struct __packed fdbar_t {
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uint32_t flvalsig;
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uint32_t flmap0;
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uint32_t flmap1;
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uint32_t flmap2;
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uint8_t reserved[0xefc - 0x20];
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uint32_t flumap1;
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};
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#define MAX_REGIONS 5
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/* regions */
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struct __packed frba_t {
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uint32_t flreg[MAX_REGIONS];
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};
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/* component section */
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struct __packed fcba_t {
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uint32_t flcomp;
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uint32_t flill;
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uint32_t flpb;
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};
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#define MAX_STRAPS 18
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/* pch strap */
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struct __packed fpsba_t {
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uint32_t pchstrp[MAX_STRAPS];
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};
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/* master */
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struct __packed fmba_t {
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uint32_t flmstr1;
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uint32_t flmstr2;
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uint32_t flmstr3;
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};
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/* processor strap */
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struct __packed fmsba_t {
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uint32_t data[8];
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};
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/* ME VSCC */
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struct vscc_t {
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uint32_t jid;
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uint32_t vscc;
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};
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struct vtba_t {
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/* Actual number of entries specified in vtl */
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struct vscc_t entry[8];
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};
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struct region_t {
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int base, limit, size;
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};
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