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u-boot/board/tplink/wdr4300
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Paul Burton 372286217f MIPS: Split I & D cache line size config 
Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-31 09:44:24 +02:00
..
Kconfig MIPS: Split I & D cache line size config 2016-05-31 09:44:24 +02:00
MAINTAINERS mips: ath79: Add support for TPLink WDR4300 2016-05-21 01:36:39 +02:00
Makefile mips: ath79: Add support for TPLink WDR4300 2016-05-21 01:36:39 +02:00
wdr4300.c mips: ath79: Add support for TPLink WDR4300 2016-05-21 01:36:39 +02:00