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372286217f
Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence. Signed-off-by: Paul Burton <paul.burton@imgtec.com> [removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
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| flash.c | ||
| Kconfig | ||
| lowlevel_init.S | ||
| MAINTAINERS | ||
| Makefile | ||
| pb1x00.c | ||
| README | ||
By Thomas.Lange@corelatus.se 2004-Oct-05 ---------------------------------------- DbAu1xx0 are development boards from AMD containing an Alchemy AU1xx0 series cpu with mips32 core. Existing cpu:s are Au1000, Au1100, Au1500 and Au1550 Limitations & comments ---------------------- Support was originally big endian only. I have not tested, but several u-boot users report working configurations in little endian mode. I named the board dbau1x00, to allow support for all three development boards ( dbau1000, dbau1100 and dbau1500 ). Now there is a new board called dbau1550 also, which should be supported RSN. I only have a dbau1000, so my testing is limited to this board. The board has two different flash banks, that can be selected via dip switch. This makes it possible to test new bootloaders without thrashing the YAMON boot loader delivered with board. NOTE! When you switch between the two boot flashes, the base addresses will be swapped. Have this in mind when you compile u-boot. CONFIG_SYS_TEXT_BASE has to match the address where u-boot is located when you actually launch. Ethernet only supported for mac0. PCMCIA only supported for slot 0, only 3.3V. PCMCIA IDE tested with Sandisk Compact Flash and IBM microdrive. ################################### ######## NOTE!!!!!! ######### ################################### If you partition a disk on another system (e.g. laptop), all bytes will be swapped on 16bit level when using PCMCIA and running cpu in big endian mode!!!! This is probably due to an error in Au1000 chip. Solution: a) Boot via network and partition disk directly from dbau1x00. The endian will then be correct. b) Partition disk on "laptop" and fill it with all files you need. Then write a simple program that endian swaps whole disk, Example: Original "laptop" byte order: B0 B1 B2 B3 B4 B5 B6 B7 B8 B9... Dbau1000 byte order will then be: B1 B0 B3 B2 B5 B4 B7 B6 B9 B8...