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Development board for headless gateway platform from Abilis Systems. Initial commit with working UART and DW GMAC. For now with generic Ethernet PHY due to problems in Realtek PHY driver. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Christian Ruppert <christian.ruppert@abilis.com> Cc: Pierrick Hascoet <pierrick.hascoet@abilis.com>
8 lines
114 B
Makefile
8 lines
114 B
Makefile
#
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# (C) Copyright 2014 Pierrick Hascoet, Abilis Systems
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += tb100.o
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