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65ea758939
This patch cleans up the Freescale MPC8308RDB Development board support.
Things fixed:
- Removed unused PCIE2 definitions from configuration
- SICR{L,H} defines used for System I/O Configuration Registers values
instead of hardcoding
- CONFIG_SYS_SCCR_PCIEXP1CM used to enable PCIE clock instead of
writing to SCCR from the board code
- sleep mode stuff removed as MPC8308 has no support for deep sleep and
PMCCR1 register. board_early_init_f() removed.
- MPC8308 has no ERRATA for DDR controller so workaround removed
- 'assignment in if statement' issues solved
- use LBLAWAR_* defines instead of hardcoding
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
98 lines
3.0 KiB
C
98 lines
3.0 KiB
C
/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
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*
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* Authors: Nick.Spence@freescale.com
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* Wilson.Lo@freescale.com
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* scottwood@freescale.com
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*
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* This files is mostly identical to the original from
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* board\freescale\mpc8315erdb\sdram.c
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc83xx.h>
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#include <asm/bitops.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Fixed sdram init -- doesn't use serial presence detect.
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*
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* This is useful for faster booting in configs where the RAM is unlikely
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* to be changed, or for things like NAND booting where space is tight.
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*/
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static long fixed_sdram(void)
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
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u32 msize_log2 = __ilog2(msize);
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out_be32(&im->sysconf.ddrlaw[0].bar,
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CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
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out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
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out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
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out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
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out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
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/* Currently we use only one CS, so disable the other bank. */
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out_be32(&im->ddr.cs_config[1], 0);
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out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
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out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
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out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
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out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
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out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
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out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
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out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
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out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
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out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
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out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
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sync();
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/* enable DDR controller */
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setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
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sync();
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return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
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}
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phys_size_t initdram(int board_type)
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize;
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if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
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return -1;
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/* DDR SDRAM */
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msize = fixed_sdram();
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/* return total bus SDRAM size(bytes) -- DDR */
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return msize;
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}
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