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343 lines
9.0 KiB
C
343 lines
9.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* EMIF: DDR3 test commands
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*
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* Copyright (C) 2012-2017 Texas Instruments Incorporated, <www.ti.com>
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*/
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#include <cpu_func.h>
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#include <env.h>
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#include <init.h>
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#include <log.h>
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#include <asm/arch/hardware.h>
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#include <asm/cache.h>
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#include <asm/emif.h>
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#include <common.h>
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#include <command.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_ARCH_KEYSTONE
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#include <asm/arch/ddr3.h>
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#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE
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#define STACKSIZE (512 << 10) /* 512 KiB */
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#define DDR_REMAP_ADDR 0x80000000
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#define ECC_START_ADDR1 ((DDR_MIN_ADDR - DDR_REMAP_ADDR) >> 17)
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#define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - \
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STACKSIZE) >> 17) - 2)
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#endif
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#define DDR_TEST_BURST_SIZE 1024
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static int ddr_memory_test(u32 start_address, u32 end_address, int quick)
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{
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u32 index_start, value, index;
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index_start = start_address;
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while (1) {
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/* Write a pattern */
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for (index = index_start;
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index < index_start + DDR_TEST_BURST_SIZE;
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index += 4)
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__raw_writel(index, index);
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/* Read and check the pattern */
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for (index = index_start;
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index < index_start + DDR_TEST_BURST_SIZE;
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index += 4) {
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value = __raw_readl(index);
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if (value != index) {
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printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
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index, value, __raw_readl(index));
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return -1;
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}
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}
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index_start += DDR_TEST_BURST_SIZE;
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if (index_start >= end_address)
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break;
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if (quick)
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continue;
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/* Write a pattern for complementary values */
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for (index = index_start;
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index < index_start + DDR_TEST_BURST_SIZE;
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index += 4)
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__raw_writel((u32)~index, index);
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/* Read and check the pattern */
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for (index = index_start;
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index < index_start + DDR_TEST_BURST_SIZE;
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index += 4) {
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value = __raw_readl(index);
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if (value != ~index) {
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printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
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index, value, __raw_readl(index));
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return -1;
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}
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}
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index_start += DDR_TEST_BURST_SIZE;
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if (index_start >= end_address)
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break;
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/* Write a pattern */
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for (index = index_start;
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index < index_start + DDR_TEST_BURST_SIZE;
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index += 2)
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__raw_writew((u16)index, index);
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/* Read and check the pattern */
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for (index = index_start;
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index < index_start + DDR_TEST_BURST_SIZE;
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index += 2) {
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value = __raw_readw(index);
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if (value != (u16)index) {
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printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
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index, value, __raw_readw(index));
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return -1;
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}
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}
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index_start += DDR_TEST_BURST_SIZE;
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if (index_start >= end_address)
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break;
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/* Write a pattern */
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for (index = index_start;
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index < index_start + DDR_TEST_BURST_SIZE;
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index += 1)
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__raw_writeb((u8)index, index);
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/* Read and check the pattern */
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for (index = index_start;
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index < index_start + DDR_TEST_BURST_SIZE;
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index += 1) {
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value = __raw_readb(index);
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if (value != (u8)index) {
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printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
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index, value, __raw_readb(index));
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return -1;
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}
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}
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index_start += DDR_TEST_BURST_SIZE;
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if (index_start >= end_address)
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break;
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}
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puts("ddr memory test PASSED!\n");
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return 0;
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}
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static int ddr_memory_compare(u32 address1, u32 address2, u32 size)
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{
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u32 index, value, index2, value2;
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for (index = address1, index2 = address2;
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index < address1 + size;
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index += 4, index2 += 4) {
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value = __raw_readl(index);
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value2 = __raw_readl(index2);
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if (value != value2) {
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printf("ddr_memory_test: Compare failed at address = 0x%x value = 0x%x, address2 = 0x%x value2 = 0x%x\n",
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index, value, index2, value2);
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return -1;
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}
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}
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puts("ddr memory compare PASSED!\n");
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return 0;
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}
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static void ddr_check_ecc_status(void)
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{
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struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
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u32 err_1b = readl(&emif->emif_1b_ecc_err_cnt);
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u32 int_status = readl(&emif->emif_irqstatus_raw_sys);
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int ecc_test = 0;
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char *env;
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env = env_get("ecc_test");
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if (env)
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ecc_test = simple_strtol(env, NULL, 0);
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puts("ECC test Status:\n");
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if (int_status & EMIF_INT_WR_ECC_ERR_SYS_MASK)
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puts("\tECC test: DDR ECC write error interrupted\n");
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if (int_status & EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK)
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if (!ecc_test)
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panic("\tECC test: DDR ECC 2-bit error interrupted");
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if (int_status & EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK)
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puts("\tECC test: DDR ECC 1-bit error interrupted\n");
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if (err_1b)
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printf("\tECC test: 1-bit ECC err count: 0x%x\n", err_1b);
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}
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static int ddr_memory_ecc_err(u32 addr, u32 ecc_err)
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{
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struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
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u32 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg);
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u32 val1, val2, val3;
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debug("Disabling D-Cache before ECC test\n");
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dcache_disable();
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invalidate_dcache_all();
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puts("Testing DDR ECC:\n");
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puts("\tECC test: Disabling DDR ECC ...\n");
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writel(0, &emif->emif_ecc_ctrl_reg);
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val1 = readl(addr);
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val2 = val1 ^ ecc_err;
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writel(val2, addr);
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val3 = readl(addr);
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#ifdef CONFIG_ARCH_KEYSTONE
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ecc_ctrl = ECC_START_ADDR1 | (ECC_END_ADDR1 << 16);
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writel(ecc_ctrl, EMIF1_BASE + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
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ddr3_enable_ecc(EMIF1_BASE, 1);
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#else
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writel(ecc_ctrl, &emif->emif_ecc_ctrl_reg);
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#endif
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printf("\tECC test: addr 0x%x, read data 0x%x, written data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
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addr, val1, val2, ecc_err, val3);
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puts("\tECC test: Enabled DDR ECC ...\n");
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val1 = readl(addr);
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printf("\tECC test: addr 0x%x, read data 0x%x\n", addr, val1);
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ddr_check_ecc_status();
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debug("Enabling D-cache back after ECC test\n");
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enable_caches();
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return 0;
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}
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static int is_addr_valid(u32 addr)
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{
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struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
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u32 start_addr, end_addr, range, ecc_ctrl;
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#ifdef CONFIG_ARCH_KEYSTONE
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ecc_ctrl = EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK;
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range = ECC_START_ADDR1 | (ECC_END_ADDR1 << 16);
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#else
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ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg);
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range = readl(&emif->emif_ecc_address_range_1);
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#endif
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/* Check in ecc address range 1 */
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if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) {
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start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16)
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+ CONFIG_SYS_SDRAM_BASE;
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end_addr = (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0xFFFF +
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CONFIG_SYS_SDRAM_BASE;
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if ((addr >= start_addr) && (addr <= end_addr))
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/* addr within ecc address range 1 */
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return 1;
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}
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/* Check in ecc address range 2 */
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if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) {
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range = readl(&emif->emif_ecc_address_range_2);
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start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16)
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+ CONFIG_SYS_SDRAM_BASE;
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end_addr = (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0xFFFF +
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CONFIG_SYS_SDRAM_BASE;
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if ((addr >= start_addr) && (addr <= end_addr))
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/* addr within ecc address range 2 */
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return 1;
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}
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return 0;
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}
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static int is_ecc_enabled(void)
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{
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struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
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u32 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg);
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return (ecc_ctrl & EMIF_ECC_CTRL_REG_ECC_EN_MASK) &&
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(ecc_ctrl & EMIF_ECC_REG_RMW_EN_MASK);
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}
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static int do_ddr_test(struct cmd_tbl *cmdtp,
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int flag, int argc, char *const argv[])
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{
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u32 start_addr, end_addr, size, ecc_err;
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if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) {
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if (!is_ecc_enabled()) {
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puts("ECC not enabled. Please Enable ECC any try again\n");
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return CMD_RET_FAILURE;
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}
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start_addr = simple_strtoul(argv[2], NULL, 16);
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ecc_err = simple_strtoul(argv[3], NULL, 16);
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if (!is_addr_valid(start_addr)) {
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puts("Invalid address. Please enter ECC supported address!\n");
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return CMD_RET_FAILURE;
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}
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ddr_memory_ecc_err(start_addr, ecc_err);
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return 0;
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}
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if (!(((argc == 4) && (strncmp(argv[1], "test", 5) == 0)) ||
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((argc == 5) && (strncmp(argv[1], "compare", 8) == 0))))
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return cmd_usage(cmdtp);
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start_addr = simple_strtoul(argv[2], NULL, 16);
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end_addr = simple_strtoul(argv[3], NULL, 16);
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if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
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(start_addr > (CONFIG_SYS_SDRAM_BASE +
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get_effective_memsize() - 1)) ||
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(end_addr < CONFIG_SYS_SDRAM_BASE) ||
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(end_addr > (CONFIG_SYS_SDRAM_BASE +
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get_effective_memsize() - 1)) || (start_addr >= end_addr)) {
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puts("Invalid start or end address!\n");
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return cmd_usage(cmdtp);
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}
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puts("Please wait ...\n");
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if (argc == 5) {
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size = simple_strtoul(argv[4], NULL, 16);
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ddr_memory_compare(start_addr, end_addr, size);
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} else {
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ddr_memory_test(start_addr, end_addr, 0);
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}
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return 0;
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}
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U_BOOT_CMD(ddr, 5, 1, do_ddr_test,
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"DDR3 test",
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"test <start_addr in hex> <end_addr in hex> - test DDR from start\n"
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" address to end address\n"
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"ddr compare <start_addr in hex> <end_addr in hex> <size in hex> -\n"
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" compare DDR data of (size) bytes from start address to end\n"
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" address\n"
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"ddr ecc_err <addr in hex> <bit_err in hex> - generate bit errors\n"
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" in DDR data at <addr>, the command will read a 32-bit data\n"
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" from <addr>, and write (data ^ bit_err) back to <addr>\n"
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);
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