mirror of
https://github.com/u-boot/u-boot.git
synced 2024-12-14 07:13:28 +08:00
662f05fcb6
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap specification does not include the Critical Delay Difference (CDD) to properly define the required rank-to-rank read command spacing after executing PHY training firmware. Following the errata workaround, at the end of data training, we get all CDD values through the MessageBlock, then re-configure the DDRC timing of WWT/WRT/RRT/RWT with comparing MAX CDD values. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> |
||
---|---|---|
.. | ||
altera | ||
fsl | ||
imx | ||
marvell | ||
microchip | ||
Kconfig |