mirror of
https://github.com/u-boot/u-boot.git
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e91907a146
This converts the following to Kconfig: CONFIG_ENV_OVERWRITE Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Rerun migration, remove some comments] Signed-off-by: Tom Rini <trini@konsulko.com>
330 lines
9.6 KiB
C
330 lines
9.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
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* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
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*
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <linux/stringify.h>
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 family */
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#ifdef CONFIG_MMC
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#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
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#define CONFIG_SYS_FSL_ESDHC_USE_PIO
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#endif
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/*
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* On-board devices
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*
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* TSEC1 is SoC TSEC
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* TSEC2 is VSC switch
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*/
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#define CONFIG_TSEC1
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#define CONFIG_VSC7385_ENET
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/*
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* SERDES
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*/
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#define CONFIG_FSL_SERDES
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#define CONFIG_FSL_SERDES1 0xe3000
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
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| DDRCDR_PZ_LOZ \
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| DDRCDR_NZ_LOZ \
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| DDRCDR_ODT \
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| DDRCDR_Q_DRN)
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/* 0x7b880001 */
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/*
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* Manually set up DDR parameters
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* consist of two chips HY5PS12621BFP-C4 from HYNIX
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*/
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#define CONFIG_SYS_DDR_SIZE 128 /* MB */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
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| CSCONFIG_ODT_RD_NEVER \
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| CSCONFIG_ODT_WR_ONLY_CURRENT \
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| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
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/* 0x80010102 */
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
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| (0 << TIMING_CFG0_WRT_SHIFT) \
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| (0 << TIMING_CFG0_RRT_SHIFT) \
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| (0 << TIMING_CFG0_WWT_SHIFT) \
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| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
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| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
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/* 0x00220802 */
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#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
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| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
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| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
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| (5 << TIMING_CFG1_CASLAT_SHIFT) \
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| (6 << TIMING_CFG1_REFREC_SHIFT) \
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| (2 << TIMING_CFG1_WRREC_SHIFT) \
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| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
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| (2 << TIMING_CFG1_WRTORD_SHIFT))
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/* 0x27256222 */
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#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
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| (4 << TIMING_CFG2_CPO_SHIFT) \
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| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
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| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
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| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
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| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
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| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
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/* 0x121048c5 */
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#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
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| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
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/* 0x03600100 */
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#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
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| SDRAM_CFG_SDRAM_TYPE_DDR2 \
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| SDRAM_CFG_DBW_32)
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/* 0x43080000 */
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
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#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
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| (0x0232 << SDRAM_MODE_SD_SHIFT))
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/* ODT 150ohm CL=3, AL=1 on SDRAM */
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#define CONFIG_SYS_DDR_MODE2 0x00000000
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/*
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* Memory test
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*/
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/*
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* The reserved memory
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
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/*
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* Initial RAM Base Address Setup
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*/
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
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#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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/* 127 64KB sectors and 8 8KB top sectors per device */
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#define CONFIG_SYS_MAX_FLASH_SECT 135
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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/*
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* NAND Flash on the Local Bus
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*/
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#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
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#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
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/* 0xFFFF8396 */
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#ifdef CONFIG_VSC7385_ENET
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#define CONFIG_TSEC2
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/* VSC7385 Base address on CS2 */
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#define CONFIG_SYS_VSC7385_BASE 0xF0000000
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#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
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/* 0xFFFE09FF */
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/* The flash address and size of the VSC7385 firmware image */
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#define CONFIG_VSC7385_IMAGE 0xFE7FE000
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#define CONFIG_VSC7385_IMAGE_SIZE 8192
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#endif
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/*
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* Serial Port
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
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/*
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* SPI on header J8
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*
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* WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
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* due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
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*/
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#ifdef CONFIG_MPC8XXX_SPI
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#define CONFIG_USE_SPIFLASH
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#endif
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/*
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* Board info - revision and where boot from
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*/
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#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
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/*
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* Config on-board RTC
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*/
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#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CONFIG_SYS_PCIE1_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
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#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
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#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
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/* enable PCIE clock */
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#define CONFIG_SYS_SCCR_PCIEXP1CM 1
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#define CONFIG_PCI_INDIRECT_BRIDGE
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#define CONFIG_PCIE
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
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/*
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* TSEC
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*/
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
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#define CONFIG_SYS_TSEC2_OFFSET 0x25000
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#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
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/*
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* TSEC ethernet configuration
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*/
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#define CONFIG_TSEC1_NAME "eTSEC0"
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#define CONFIG_TSEC2_NAME "eTSEC1"
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 1
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC2_FLAGS TSEC_GIGABIT
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/* Options are: eTSEC[0-1] */
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#define CONFIG_ETHPRIME "eTSEC0"
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/*
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* Environment
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*/
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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/*
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* Environment Configuration
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*/
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#endif
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#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"consoledev=ttyS0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs}" \
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" console=${consoledev},${baudrate}\0" \
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"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"addmisc=setenv bootargs ${bootargs}\0" \
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"kernel_addr=FE080000\0" \
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"fdt_addr=FE280000\0" \
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"ramdisk_addr=FE290000\0" \
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"u-boot=mpc8308rdb/u-boot.bin\0" \
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"kernel_addr_r=1000000\0" \
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"fdt_addr_r=C00000\0" \
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"hostname=mpc8308rdb\0" \
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"bootfile=mpc8308rdb/uImage\0" \
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"fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
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"rootpath=/opt/eldk-4.2/ppc_6xx\0" \
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"flash_self=run ramargs addip addtty addmtd addmisc;" \
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"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
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"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
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"bootm ${kernel_addr} - ${fdt_addr}\0" \
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"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
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"tftp ${fdt_addr_r} ${fdtfile};" \
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"run nfsargs addip addtty addmtd addmisc;" \
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"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
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"bootcmd=run flash_self\0" \
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"load=tftp ${loadaddr} ${u-boot}\0" \
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"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
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" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
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" +${filesize};cp.b ${fileaddr} " \
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__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
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"upd=run load update\0" \
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#endif /* __CONFIG_H */
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