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414 lines
9.3 KiB
C
414 lines
9.3 KiB
C
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <clps7111.h>
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#include <asm/proc-armv/ptrace.h>
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#include <asm/hardware.h>
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#ifndef CONFIG_NETARM
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/* we always count down the max. */
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#define TIMER_LOAD_VAL 0xffff
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/* macro to read the 16 bit timer */
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#define READ_TIMER (IO_TC1D & 0xffff)
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#else
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#define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
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#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
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#define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
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#define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
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#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
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#endif
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#ifdef CONFIG_S3C4510B
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/* require interrupts for the S3C4510B */
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# ifndef CONFIG_USE_IRQ
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# error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
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# else
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static struct _irq_handler IRQ_HANDLER[N_IRQS];
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# endif
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#endif /* CONFIG_S3C4510B */
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#ifdef CONFIG_USE_IRQ
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/* enable IRQ/FIQ interrupts */
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void enable_interrupts (void)
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{
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unsigned long temp;
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__asm__ __volatile__("mrs %0, cpsr\n"
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"bic %0, %0, #0x80\n"
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"msr cpsr_c, %0"
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: "=r" (temp)
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:
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: "memory");
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}
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/*
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* disable IRQ/FIQ interrupts
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* returns true if interrupts had been enabled before we disabled them
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*/
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int disable_interrupts (void)
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{
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unsigned long old,temp;
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__asm__ __volatile__("mrs %0, cpsr\n"
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"orr %1, %0, #0x80\n"
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"msr cpsr_c, %1"
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: "=r" (old), "=r" (temp)
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:
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: "memory");
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return (old & 0x80) == 0;
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}
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#else /* CONFIG_USE_IRQ */
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void enable_interrupts (void)
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{
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return;
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}
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int disable_interrupts (void)
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{
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return 0;
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}
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#endif
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void bad_mode (void)
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{
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panic ("Resetting CPU ...\n");
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reset_cpu (0);
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}
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void show_regs (struct pt_regs *regs)
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{
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unsigned long flags;
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const char *processor_modes[] =
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{ "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26",
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"UK6_26", "UK7_26",
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"UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26",
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"UK14_26", "UK15_26",
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"USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32",
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"UK6_32", "ABT_32",
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"UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32",
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"UK14_32", "SYS_32"
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};
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flags = condition_codes (regs);
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printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
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"sp : %08lx ip : %08lx fp : %08lx\n",
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instruction_pointer (regs),
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regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
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printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
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regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
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printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
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regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
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printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
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regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
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printf ("Flags: %c%c%c%c",
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flags & CC_N_BIT ? 'N' : 'n',
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flags & CC_Z_BIT ? 'Z' : 'z',
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flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
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printf (" IRQs %s FIQs %s Mode %s%s\n",
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interrupts_enabled (regs) ? "on" : "off",
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fast_interrupts_enabled (regs) ? "on" : "off",
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processor_modes[processor_mode (regs)],
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thumb_mode (regs) ? " (T)" : "");
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}
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void do_undefined_instruction (struct pt_regs *pt_regs)
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{
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printf ("undefined instruction\n");
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show_regs (pt_regs);
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bad_mode ();
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}
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void do_software_interrupt (struct pt_regs *pt_regs)
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{
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printf ("software interrupt\n");
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show_regs (pt_regs);
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bad_mode ();
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}
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void do_prefetch_abort (struct pt_regs *pt_regs)
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{
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printf ("prefetch abort\n");
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show_regs (pt_regs);
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bad_mode ();
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}
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void do_data_abort (struct pt_regs *pt_regs)
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{
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printf ("data abort\n");
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show_regs (pt_regs);
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bad_mode ();
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}
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void do_not_used (struct pt_regs *pt_regs)
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{
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printf ("not used\n");
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show_regs (pt_regs);
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bad_mode ();
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}
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void do_fiq (struct pt_regs *pt_regs)
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{
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printf ("fast interrupt request\n");
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show_regs (pt_regs);
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bad_mode ();
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}
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void do_irq (struct pt_regs *pt_regs)
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{
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#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
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printf ("interrupt request\n");
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show_regs (pt_regs);
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bad_mode ();
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#elif defined(CONFIG_S3C4510B)
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unsigned int pending;
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while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) { /* sentinal value for no pending interrutps */
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IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
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/* clear pending interrupt */
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PUT_REG( REG_INTPEND, (1<<(pending>>2)));
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}
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#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
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/* No do_irq() for IntegratorAP/CM720T as yet */
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#else
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#error do_irq() not defined for this CPU type
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#endif
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}
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#ifdef CONFIG_S3C4510B
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static void default_isr( void *data) {
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printf ("default_isr(): called for IRQ %d\n", (int)data);
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}
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static void timer_isr( void *data) {
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unsigned int *pTime = (unsigned int *)data;
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(*pTime)++;
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if ( !(*pTime % (CFG_HZ/4))) {
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/* toggle LED 0 */
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PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
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}
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}
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#endif
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#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
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/* Use IntegratorAP routines in board/integratorap.c */
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#else
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static ulong timestamp;
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static ulong lastdec;
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int interrupt_init (void)
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{
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#if defined(CONFIG_NETARM)
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/* disable all interrupts */
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IRQEN = 0;
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/* operate timer 2 in non-prescale mode */
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TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CFG_HZ) |
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NETARM_GEN_TCTL_ENABLE |
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NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
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/* set timer 2 counter */
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lastdec = TIMER_LOAD_VAL;
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#elif defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
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/* disable all interrupts */
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IO_INTMR1 = 0;
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/* operate timer 1 in prescale mode */
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IO_SYSCON1 |= SYSCON1_TC1M;
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/* select 2kHz clock source for timer 1 */
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IO_SYSCON1 &= ~SYSCON1_TC1S;
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/* set timer 1 counter */
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lastdec = IO_TC1D = TIMER_LOAD_VAL;
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#elif defined(CONFIG_S3C4510B)
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int i;
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/* install default interrupt handlers */
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for ( i = 0; i < N_IRQS; i++) {
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IRQ_HANDLER[i].m_data = (void *)i;
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IRQ_HANDLER[i].m_func = default_isr;
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}
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/* configure interrupts for IRQ mode */
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PUT_REG( REG_INTMODE, 0x0);
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/* clear any pending interrupts */
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PUT_REG( REG_INTPEND, 0x1FFFFF);
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lastdec = 0;
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/* install interrupt handler for timer */
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IRQ_HANDLER[INT_TIMER0].m_data = (void *)×tamp;
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IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
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/* configure free running timer 0 */
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PUT_REG( REG_TMOD, 0x0);
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/* Stop timer 0 */
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CLR_REG( REG_TMOD, TM0_RUN);
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/* Configure for interval mode */
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CLR_REG( REG_TMOD, TM1_TOGGLE);
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/*
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* Load Timer data register with count down value.
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* count_down_val = CFG_SYS_CLK_FREQ/CFG_HZ
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*/
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PUT_REG( REG_TDATA0, (CFG_SYS_CLK_FREQ / CFG_HZ));
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/*
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* Enable global interrupt
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* Enable timer0 interrupt
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*/
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CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
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/* Start timer */
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SET_REG( REG_TMOD, TM0_RUN);
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#else
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#error No interrupt_init() defined for this CPU type
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#endif
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timestamp = 0;
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return (0);
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}
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#endif /* ! IntegratorAP */
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/*
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* timer without interrupts
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*/
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#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
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void reset_timer (void)
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{
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reset_timer_masked ();
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}
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ulong get_timer (ulong base)
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{
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return get_timer_masked () - base;
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}
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void set_timer (ulong t)
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{
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timestamp = t;
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}
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void udelay (unsigned long usec)
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{
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ulong tmo;
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tmo = usec / 1000;
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tmo *= CFG_HZ;
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tmo /= 1000;
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tmo += get_timer (0);
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while (get_timer_masked () < tmo)
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/*NOP*/;
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}
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void reset_timer_masked (void)
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{
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/* reset time */
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lastdec = READ_TIMER;
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timestamp = 0;
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}
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ulong get_timer_masked (void)
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{
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ulong now = READ_TIMER;
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if (lastdec >= now) {
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/* normal mode */
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timestamp += lastdec - now;
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} else {
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/* we have an overflow ... */
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timestamp += lastdec + TIMER_LOAD_VAL - now;
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}
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lastdec = now;
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return timestamp;
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}
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void udelay_masked (unsigned long usec)
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{
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ulong tmo;
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ulong endtime;
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signed long diff;
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if (usec >= 1000) {
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tmo = usec / 1000;
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tmo *= CFG_HZ;
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tmo /= 1000;
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} else {
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tmo = usec * CFG_HZ;
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tmo /= (1000*1000);
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}
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endtime = get_timer_masked () + tmo;
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do {
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ulong now = get_timer_masked ();
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diff = endtime - now;
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} while (diff >= 0);
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}
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#elif defined(CONFIG_S3C4510B)
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ulong get_timer (ulong base)
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{
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return timestamp - base;
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}
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void udelay (unsigned long usec)
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{
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u32 ticks;
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ticks = (usec * CFG_HZ) / 1000000;
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ticks += get_timer (0);
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while (get_timer (0) < ticks)
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/*NOP*/;
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}
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#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
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/* No timer routines for IntegratorAP/CM720T as yet */
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#else
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#error Timer routines not defined for this CPU type
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#endif
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