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76c2ff3e5f
For levels equal to the maximum value, the duty cycle must be equal to the period. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
81 lines
2.5 KiB
C
81 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Test for panel uclass
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*
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* Copyright (c) 2018 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <common.h>
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#include <backlight.h>
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#include <dm.h>
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#include <panel.h>
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#include <video.h>
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#include <asm/gpio.h>
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#include <asm/test.h>
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#include <dm/test.h>
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#include <power/regulator.h>
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#include <test/test.h>
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#include <test/ut.h>
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/* Basic test of the panel uclass */
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static int dm_test_panel(struct unit_test_state *uts)
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{
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struct udevice *dev, *pwm, *gpio, *reg;
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uint period_ns;
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uint duty_ns;
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bool enable;
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bool polarity;
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ut_assertok(uclass_first_device_err(UCLASS_PANEL, &dev));
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ut_assertok(uclass_first_device_err(UCLASS_PWM, &pwm));
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ut_assertok(uclass_get_device(UCLASS_GPIO, 1, &gpio));
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ut_assertok(regulator_get_by_platname("VDD_EMMC_1.8V", ®));
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ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
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&enable, &polarity));
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ut_asserteq(false, enable);
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ut_asserteq(false, regulator_get_enable(reg));
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ut_assertok(panel_enable_backlight(dev));
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ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
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&enable, &polarity));
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ut_asserteq(1000, period_ns);
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ut_asserteq(170 * 1000 / 255, duty_ns);
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ut_asserteq(true, enable);
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ut_asserteq(false, polarity);
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ut_asserteq(1, sandbox_gpio_get_value(gpio, 1));
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ut_asserteq(true, regulator_get_enable(reg));
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ut_assertok(panel_set_backlight(dev, 40));
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ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
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&enable, &polarity));
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ut_asserteq(64 * 1000 / 255, duty_ns);
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ut_assertok(panel_set_backlight(dev, BACKLIGHT_MAX));
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ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
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&enable, &polarity));
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ut_asserteq(255 * 1000 / 255, duty_ns);
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ut_assertok(panel_set_backlight(dev, BACKLIGHT_MIN));
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ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
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&enable, &polarity));
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ut_asserteq(0 * 1000 / 255, duty_ns);
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ut_asserteq(1, sandbox_gpio_get_value(gpio, 1));
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ut_assertok(panel_set_backlight(dev, BACKLIGHT_DEFAULT));
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ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
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&enable, &polarity));
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ut_asserteq(true, enable);
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ut_asserteq(170 * 1000 / 255, duty_ns);
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ut_assertok(panel_set_backlight(dev, BACKLIGHT_OFF));
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ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
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&enable, &polarity));
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ut_asserteq(0 * 1000 / 255, duty_ns);
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ut_asserteq(0, sandbox_gpio_get_value(gpio, 1));
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ut_asserteq(false, regulator_get_enable(reg));
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return 0;
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}
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DM_TEST(dm_test_panel, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
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