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addb2e1650
code and in SoC code). Boards using the old way have CFG_NAND_LEGACY and BOARDLIBS = drivers/nand_legacy/libnand_legacy.a added. Build breakage for NETTA.ERR and NETTA_ISDN - will go away when the new NAND support is implemented for these boards.
533 lines
16 KiB
C
533 lines
16 KiB
C
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Pantelis Antoniou, Intracom S.A., panto@intracom.gr
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* U-Boot port on NetVia board
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
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#define CONFIG_NETVIA 1 /* ...on a NetVia board */
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#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#else
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#define CONFIG_8xx_CONS_NONE
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#define CONFIG_MAX3100_SERIAL
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#endif
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#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
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#define CONFIG_XIN 10000000
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#define CONFIG_8xx_GCLK_FREQ 80000000
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
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#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"tftpboot; " \
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"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
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"bootm"
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#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_STATUS_LED 1 /* Status LED enabled */
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#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
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#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
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#endif
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#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
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#undef CONFIG_MAC_PARTITION
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#undef CONFIG_DOS_PARTITION
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#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
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#define CONFIG_COMMANDS_BASE ( CONFIG_CMD_DFL | \
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CFG_CMD_DHCP | \
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CFG_CMD_PING )
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#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
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#define CONFIG_COMMANDS (CONFIG_COMMANDS_BASE | CFG_CMD_NAND)
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#else
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#define CONFIG_COMMANDS CONFIG_COMMANDS_BASE
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#endif
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#define CONFIG_BOARD_EARLY_INIT_F 1
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#define CONFIG_MISC_INIT_R
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0300000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xFF000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x40000000
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#if defined(DEBUG)
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#else
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#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#endif
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_SECT_SIZE 0x10000
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
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#define CFG_ENV_OFFSET 0
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#define CFG_ENV_SIZE 0x4000
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#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000)
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#define CFG_ENV_OFFSET_REDUND 0
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#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#ifndef CONFIG_CAN_DRIVER
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#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
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#else /* we must activate GPL5 in the SIUMCR for CAN */
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#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
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#endif /* CONFIG_CAN_DRIVER */
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register 11-27
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*-----------------------------------------------------------------------
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*/
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#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit
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*
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*
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*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#if CONFIG_8xx_GCLK_FREQ == 50000000
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#define CFG_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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#define CFG_SCCR (SCCR_TBS | \
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00)
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#elif CONFIG_8xx_GCLK_FREQ == 80000000
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#define CFG_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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#define CFG_SCCR (SCCR_TBS | \
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00 | SCCR_EBDF01)
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#endif
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
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/*#define CFG_DER 0x2002000F*/
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#define CFG_DER 0
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
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/* used to re-map FLASH both when starting from SRAM or FLASH:
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* restrict access enough to keep SRAM working (if any)
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* but not too much to meddle with FLASH accesses
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*/
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#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
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#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
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/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
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#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
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#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
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/*
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* BR3 and OR3 (SDRAM)
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*
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*/
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#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
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#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
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/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
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#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
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#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
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#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
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/*
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* Memory Periodic Timer Prescaler
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*/
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/* periodic timer for refresh */
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#define CFG_MAMR_PTA 208
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/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
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#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
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/*
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* MAMR settings for SDRAM
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*/
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/* 9 column SDRAM */
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#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
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MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/* Ethernet at SCC2 */
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#define CONFIG_SCC2_ENET
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#define CONFIG_ARTOS /* include ARTOS support */
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/****************************************************************/
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#define DSP_SIZE 0x00010000 /* 64K */
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#define FPGA_SIZE 0x00010000 /* 64K */
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#define DSP0_BASE 0xF1000000
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#define DSP1_BASE (DSP0_BASE + DSP_SIZE)
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#define FPGA_BASE (DSP1_BASE + DSP_SIZE)
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#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
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#define ER_SIZE 0x00010000 /* 64K */
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#define ER_BASE (FPGA_BASE + FPGA_SIZE)
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#define NAND_SIZE 0x00010000 /* 64K */
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#define NAND_BASE (ER_BASE + ER_SIZE)
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#endif
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/****************************************************************/
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#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
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#define STATUS_LED_BIT 0x00000001 /* bit 31 */
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#define STATUS_LED_PERIOD (CFG_HZ / 2)
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#define STATUS_LED_STATE STATUS_LED_BLINKING
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#define STATUS_LED_BIT1 0x00000002 /* bit 30 */
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#define STATUS_LED_PERIOD1 (CFG_HZ / 2)
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#define STATUS_LED_STATE1 STATUS_LED_OFF
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#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
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#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
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#endif
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/*****************************************************************************/
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#define CFG_NAND_LEGACY
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#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
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/* NAND */
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#define CFG_NAND_BASE NAND_BASE
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#define CONFIG_MTD_NAND_ECC_JFFS2
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#define CFG_MAX_NAND_DEVICE 1
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#define SECTORSIZE 512
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define NAND_ChipID_UNKNOWN 0x00
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#define NAND_MAX_FLOORS 1
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#define NAND_MAX_CHIPS 1
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#define NAND_DISABLE_CE(nand) \
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do { \
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(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0040; \
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} while(0)
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#define NAND_ENABLE_CE(nand) \
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do { \
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(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0040; \
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} while(0)
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#define NAND_CTL_CLRALE(nandptr) \
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do { \
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(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0100; \
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} while(0)
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#define NAND_CTL_SETALE(nandptr) \
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do { \
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(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0100; \
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} while(0)
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#define NAND_CTL_CLRCLE(nandptr) \
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do { \
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(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0080; \
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} while(0)
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#define NAND_CTL_SETCLE(nandptr) \
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do { \
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(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0080; \
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} while(0)
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#define NAND_WAIT_READY(nand) \
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do { \
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while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x100) == 0) \
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; \
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} while (0)
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#define WRITE_NAND_COMMAND(d, adr) \
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do { \
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*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
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} while(0)
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#define WRITE_NAND_ADDRESS(d, adr) \
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do { \
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*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
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} while(0)
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#define WRITE_NAND(d, adr) \
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do { \
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*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
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} while(0)
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#define READ_NAND(adr) \
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((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
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#endif
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/*****************************************************************************/
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#ifndef __ASSEMBLY__
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#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
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/* LEDs */
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/* last value written to the external register; we cannot read back */
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extern unsigned int last_er_val;
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/* led_id_t is unsigned long mask */
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typedef unsigned int led_id_t;
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static inline void __led_init(led_id_t mask, int state)
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{
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unsigned int new_er_val;
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if (state)
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new_er_val = last_er_val & ~mask;
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else
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new_er_val = last_er_val | mask;
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*(volatile unsigned int *)ER_BASE = new_er_val;
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last_er_val = new_er_val;
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}
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static inline void __led_toggle(led_id_t mask)
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{
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unsigned int new_er_val;
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new_er_val = last_er_val ^ mask;
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*(volatile unsigned int *)ER_BASE = new_er_val;
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last_er_val = new_er_val;
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}
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static inline void __led_set(led_id_t mask, int state)
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{
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unsigned int new_er_val;
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if (state)
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new_er_val = last_er_val & ~mask;
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else
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new_er_val = last_er_val | mask;
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*(volatile unsigned int *)ER_BASE = new_er_val;
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last_er_val = new_er_val;
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}
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/* MAX3100 console */
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#define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
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#define MAX3100_SPI_RXD_BIT 0x00000008
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#define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
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#define MAX3100_SPI_TXD_BIT 0x00000004
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#define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
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#define MAX3100_SPI_CLK_BIT 0x00000002
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#define MAX3100_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat)
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#define MAX3100_CS_BIT 0x0010
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#endif
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#endif
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/*************************************************************************************************/
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#endif /* __CONFIG_H */
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