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https://github.com/u-boot/u-boot.git
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
227 lines
5.7 KiB
C
227 lines
5.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright Altera Corporation (C) 2012-2015
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*/
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#ifndef _SEQUENCER_H_
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#define _SEQUENCER_H_
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#define RW_MGR_NUM_DM_PER_WRITE_GROUP (rwcfg->mem_data_mask_width \
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/ rwcfg->mem_if_write_dqs_width)
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#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (rwcfg->true_mem_data_mask_width \
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/ rwcfg->mem_if_write_dqs_width)
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#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (rwcfg->mem_if_read_dqs_width \
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/ rwcfg->mem_if_write_dqs_width)
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#define NUM_RANKS_PER_SHADOW_REG (rwcfg->mem_number_of_ranks / NUM_SHADOW_REGS)
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#define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0
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#define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400
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#define RW_MGR_RESET_READ_DATAPATH_OFFSET 0x1000
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#define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET 0x1400
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#define RW_MGR_INST_ROM_WRITE_OFFSET 0x1800
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#define RW_MGR_AC_ROM_WRITE_OFFSET 0x1C00
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#define NUM_SHADOW_REGS 1
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#define RW_MGR_RANK_NONE 0xFF
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#define RW_MGR_RANK_ALL 0x00
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#define RW_MGR_ODT_MODE_OFF 0
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#define RW_MGR_ODT_MODE_READ_WRITE 1
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#define NUM_CALIB_REPEAT 1
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#define NUM_READ_TESTS 7
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#define NUM_READ_PB_TESTS 7
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#define NUM_WRITE_TESTS 15
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#define NUM_WRITE_PB_TESTS 31
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#define PASS_ALL_BITS 1
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#define PASS_ONE_BIT 0
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/* calibration stages */
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#define CAL_STAGE_NIL 0
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#define CAL_STAGE_VFIFO 1
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#define CAL_STAGE_WLEVEL 2
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#define CAL_STAGE_LFIFO 3
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#define CAL_STAGE_WRITES 4
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#define CAL_STAGE_FULLTEST 5
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#define CAL_STAGE_REFRESH 6
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#define CAL_STAGE_CAL_SKIPPED 7
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#define CAL_STAGE_CAL_ABORTED 8
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#define CAL_STAGE_VFIFO_AFTER_WRITES 9
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/* calibration substages */
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#define CAL_SUBSTAGE_NIL 0
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#define CAL_SUBSTAGE_GUARANTEED_READ 1
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#define CAL_SUBSTAGE_DQS_EN_PHASE 2
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#define CAL_SUBSTAGE_VFIFO_CENTER 3
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#define CAL_SUBSTAGE_WORKING_DELAY 1
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#define CAL_SUBSTAGE_LAST_WORKING_DELAY 2
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#define CAL_SUBSTAGE_WLEVEL_COPY 3
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#define CAL_SUBSTAGE_WRITES_CENTER 1
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#define CAL_SUBSTAGE_READ_LATENCY 1
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#define CAL_SUBSTAGE_REFRESH 1
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#define SCC_MGR_GROUP_COUNTER_OFFSET 0x0000
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#define SCC_MGR_DQS_IN_DELAY_OFFSET 0x0100
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#define SCC_MGR_DQS_EN_PHASE_OFFSET 0x0200
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#define SCC_MGR_DQS_EN_DELAY_OFFSET 0x0300
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#define SCC_MGR_DQDQS_OUT_PHASE_OFFSET 0x0400
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#define SCC_MGR_OCT_OUT1_DELAY_OFFSET 0x0500
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#define SCC_MGR_IO_OUT1_DELAY_OFFSET 0x0700
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#define SCC_MGR_IO_IN_DELAY_OFFSET 0x0900
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/* HHP-HPS-specific versions of some commands */
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#define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET 0x0600
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#define SCC_MGR_IO_OE_DELAY_OFFSET 0x0800
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#define SCC_MGR_HHP_GLOBALS_OFFSET 0x0A00
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#define SCC_MGR_HHP_RFILE_OFFSET 0x0B00
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#define SCC_MGR_AFI_CAL_INIT_OFFSET 0x0D00
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#define SDR_PHYGRP_SCCGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x0)
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#define SDR_PHYGRP_PHYMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x1000)
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#define SDR_PHYGRP_RWMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x2000)
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#define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4000)
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#define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4800)
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#define PHY_MGR_CAL_RESET (0)
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#define PHY_MGR_CAL_SUCCESS (1)
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#define PHY_MGR_CAL_FAIL (2)
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#define CALIB_SKIP_DELAY_LOOPS (1 << 0)
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#define CALIB_SKIP_ALL_BITS_CHK (1 << 1)
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#define CALIB_SKIP_DELAY_SWEEPS (1 << 2)
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#define CALIB_SKIP_VFIFO (1 << 3)
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#define CALIB_SKIP_LFIFO (1 << 4)
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#define CALIB_SKIP_WLEVEL (1 << 5)
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#define CALIB_SKIP_WRITES (1 << 6)
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#define CALIB_SKIP_FULL_TEST (1 << 7)
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#define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | \
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CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \
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CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
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#define CALIB_IN_RTL_SIM (1 << 8)
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/* Scan chain manager command addresses */
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#define READ_SCC_OCT_OUT2_DELAY 0
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#define READ_SCC_DQ_OUT2_DELAY 0
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#define READ_SCC_DQS_IO_OUT2_DELAY 0
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#define READ_SCC_DM_IO_OUT2_DELAY 0
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/* HHP-HPS-specific values */
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#define SCC_MGR_HHP_EXTRAS_OFFSET 0
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#define SCC_MGR_HHP_DQSE_MAP_OFFSET 1
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/* PHY Debug mode flag constants */
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#define PHY_DEBUG_IN_DEBUG_MODE 0x00000001
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#define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002
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#define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004
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#define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008
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#define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
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#define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
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struct socfpga_sdr_rw_load_manager {
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u32 load_cntr0;
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u32 load_cntr1;
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u32 load_cntr2;
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u32 load_cntr3;
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};
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struct socfpga_sdr_rw_load_jump_manager {
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u32 load_jump_add0;
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u32 load_jump_add1;
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u32 load_jump_add2;
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u32 load_jump_add3;
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};
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struct socfpga_sdr_reg_file {
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u32 signature;
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u32 debug_data_addr;
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u32 cur_stage;
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u32 fom;
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u32 failing_stage;
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u32 debug1;
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u32 debug2;
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u32 dtaps_per_ptap;
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u32 trk_sample_count;
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u32 trk_longidle;
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u32 delays;
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u32 trk_rw_mgr_addr;
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u32 trk_read_dqs_width;
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u32 trk_rfsh;
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};
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/* parameter variable holder */
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struct param_type {
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u32 read_correct_mask;
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u32 read_correct_mask_vg;
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u32 write_correct_mask;
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u32 write_correct_mask_vg;
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};
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/* global variable holder */
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struct gbl_type {
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uint32_t phy_debug_mode_flags;
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/* current read latency */
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uint32_t curr_read_lat;
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/* error code */
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uint32_t error_substage;
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uint32_t error_stage;
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uint32_t error_group;
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/* figure-of-merit in, figure-of-merit out */
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uint32_t fom_in;
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uint32_t fom_out;
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/*USER Number of RW Mgr NOP cycles between
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write command and write data */
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uint32_t rw_wl_nop_cycles;
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};
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struct socfpga_sdr_scc_mgr {
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u32 dqs_ena;
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u32 dqs_io_ena;
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u32 dq_ena;
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u32 dm_ena;
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u32 __padding1[4];
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u32 update;
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u32 __padding2[7];
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u32 active_rank;
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};
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/* PHY manager configuration registers. */
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struct socfpga_phy_mgr_cfg {
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u32 phy_rlat;
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u32 reset_mem_stbl;
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u32 mux_sel;
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u32 cal_status;
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u32 cal_debug_info;
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u32 vfifo_rd_en_ovrd;
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u32 afi_wlat;
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u32 afi_rlat;
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};
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/* PHY manager command addresses. */
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struct socfpga_phy_mgr_cmd {
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u32 inc_vfifo_fr;
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u32 inc_vfifo_hard_phy;
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u32 fifo_reset;
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u32 inc_vfifo_fr_hr;
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u32 inc_vfifo_qr;
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};
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struct socfpga_data_mgr {
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u32 __padding1;
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u32 t_wl_add;
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u32 mem_t_add;
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u32 t_rl_add;
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};
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#endif /* _SEQUENCER_H_ */
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