mirror of
https://github.com/u-boot/u-boot.git
synced 2024-11-26 21:54:37 +08:00
1baa4e72c6
Took these values directly from the kernel dts files. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
220 lines
5.0 KiB
Plaintext
220 lines
5.0 KiB
Plaintext
#include "skeleton.dtsi"
|
|
|
|
/ {
|
|
compatible = "nvidia,tegra30";
|
|
|
|
tegra_car: clock {
|
|
compatible = "nvidia,tegra30-car";
|
|
reg = <0x60006000 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
apbdma: dma {
|
|
compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
|
|
reg = <0x6000a000 0x1400>;
|
|
interrupts = <0 104 0x04
|
|
0 105 0x04
|
|
0 106 0x04
|
|
0 107 0x04
|
|
0 108 0x04
|
|
0 109 0x04
|
|
0 110 0x04
|
|
0 111 0x04
|
|
0 112 0x04
|
|
0 113 0x04
|
|
0 114 0x04
|
|
0 115 0x04
|
|
0 116 0x04
|
|
0 117 0x04
|
|
0 118 0x04
|
|
0 119 0x04
|
|
0 128 0x04
|
|
0 129 0x04
|
|
0 130 0x04
|
|
0 131 0x04
|
|
0 132 0x04
|
|
0 133 0x04
|
|
0 134 0x04
|
|
0 135 0x04
|
|
0 136 0x04
|
|
0 137 0x04
|
|
0 138 0x04
|
|
0 139 0x04
|
|
0 140 0x04
|
|
0 141 0x04
|
|
0 142 0x04
|
|
0 143 0x04>;
|
|
clocks = <&tegra_car 34>;
|
|
};
|
|
|
|
gpio: gpio {
|
|
compatible = "nvidia,tegra30-gpio";
|
|
reg = <0x6000d000 0x1000>;
|
|
interrupts = <0 32 0x04
|
|
0 33 0x04
|
|
0 34 0x04
|
|
0 35 0x04
|
|
0 55 0x04
|
|
0 87 0x04
|
|
0 89 0x04
|
|
0 125 0x04>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
i2c@7000c000 {
|
|
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
|
|
reg = <0x7000c000 0x100>;
|
|
interrupts = <0 38 0x04>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 12>, <&tegra_car 182>;
|
|
clock-names = "div-clk", "fast-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000c400 {
|
|
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
|
|
reg = <0x7000c400 0x100>;
|
|
interrupts = <0 84 0x04>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 54>, <&tegra_car 182>;
|
|
clock-names = "div-clk", "fast-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000c500 {
|
|
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
|
|
reg = <0x7000c500 0x100>;
|
|
interrupts = <0 92 0x04>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 67>, <&tegra_car 182>;
|
|
clock-names = "div-clk", "fast-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000c700 {
|
|
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
|
|
reg = <0x7000c700 0x100>;
|
|
interrupts = <0 120 0x04>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 103>, <&tegra_car 182>;
|
|
clock-names = "div-clk", "fast-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000d000 {
|
|
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
|
|
reg = <0x7000d000 0x100>;
|
|
interrupts = <0 53 0x04>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 47>, <&tegra_car 182>;
|
|
clock-names = "div-clk", "fast-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000d400 {
|
|
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
|
reg = <0x7000d400 0x200>;
|
|
interrupts = <0 59 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 15>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 41>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000d600 {
|
|
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
|
reg = <0x7000d600 0x200>;
|
|
interrupts = <0 82 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 16>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 44>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000d800 {
|
|
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
|
reg = <0x7000d480 0x200>;
|
|
interrupts = <0 83 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 17>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 46>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000da00 {
|
|
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
|
reg = <0x7000da00 0x200>;
|
|
interrupts = <0 93 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 18>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 68>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000dc00 {
|
|
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
|
reg = <0x7000dc00 0x200>;
|
|
interrupts = <0 94 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 27>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 104>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000de00 {
|
|
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
|
reg = <0x7000de00 0x200>;
|
|
interrupts = <0 79 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 28>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car 105>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@78000000 {
|
|
compatible = "nvidia,tegra30-sdhci";
|
|
reg = <0x78000000 0x200>;
|
|
interrupts = <0 14 0x04>;
|
|
clocks = <&tegra_car 14>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@78000200 {
|
|
compatible = "nvidia,tegra30-sdhci";
|
|
reg = <0x78000200 0x200>;
|
|
interrupts = <0 15 0x04>;
|
|
clocks = <&tegra_car 9>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@78000400 {
|
|
compatible = "nvidia,tegra30-sdhci";
|
|
reg = <0x78000400 0x200>;
|
|
interrupts = <0 19 0x04>;
|
|
clocks = <&tegra_car 69>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@78000600 {
|
|
compatible = "nvidia,tegra30-sdhci";
|
|
reg = <0x78000600 0x200>;
|
|
interrupts = <0 31 0x04>;
|
|
clocks = <&tegra_car 15>;
|
|
status = "disabled";
|
|
};
|
|
};
|