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540b5af281
Create a common configuration file for all exynos5250 based boards. Going forward we will be using DT based driver discovery for all the boards based on Exynos5. The different boards added will have there own config.h files which internally will include this file and specify their specific DT files. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
301 lines
8.4 KiB
C
301 lines
8.4 KiB
C
/*
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* Copyright (C) 2012 Samsung Electronics
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*
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* Configuration settings for the SAMSUNG EXYNOS5250 board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_SAMSUNG /* in a SAMSUNG core */
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#define CONFIG_S5P /* S5P Family */
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#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
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#define CONFIG_SMDK5250 /* which is in a SMDK5250 */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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/* Enable fdt support for Exynos5250 */
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#define CONFIG_ARCH_DEVICE_TREE exynos5250
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#define CONFIG_OF_CONTROL
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#define CONFIG_OF_SEPARATE
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/* Keep L2 Cache Disabled */
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#define CONFIG_SYS_DCACHE_OFF
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define CONFIG_SYS_TEXT_BASE 0x43E00000
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/* input clock of PLL: SMDK5250 has 24MHz input clock */
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#define CONFIG_SYS_CLK_FREQ 24000000
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_INITRD_TAG
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#define CONFIG_CMDLINE_EDITING
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/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
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#define MACH_TYPE_SMDK5250 3774
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#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
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/* Power Down Modes */
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#define S5P_CHECK_SLEEP 0x00000BAD
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#define S5P_CHECK_DIDLE 0xBAD00000
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#define S5P_CHECK_LPA 0xABAD0000
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/* Offset for inform registers */
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#define INFORM0_OFFSET 0x800
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#define INFORM1_OFFSET 0x804
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
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/* select serial console configuration */
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#define CONFIG_SERIAL3 /* use SERIAL 3 */
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#define CONFIG_BAUDRATE 115200
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#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
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#define TZPC_BASE_OFFSET 0x10000
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/* SD/MMC configuration */
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#define CONFIG_GENERIC_MMC
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#define CONFIG_MMC
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#define CONFIG_SDHCI
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#define CONFIG_S5P_SDHCI
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#define CONFIG_BOARD_EARLY_INIT_F
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/* PWM */
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#define CONFIG_PWM
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* Command definition*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_NET
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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/* USB */
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#define CONFIG_CMD_USB
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_EXYNOS
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#define CONFIG_USB_STORAGE
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/* MMC SPL */
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#define CONFIG_SPL
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#define COPY_BL2_FNPTR_ADDR 0x02020030
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/* specific .lds file */
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#define CONFIG_SPL_LDSCRIPT "board/samsung/smdk5250/smdk5250-uboot-spl.lds"
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#define CONFIG_SPL_TEXT_BASE 0x02023400
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#define CONFIG_SPL_MAX_SIZE (14 * 1024)
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#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_SYS_PROMPT "SMDK5250 # "
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* memtest works on */
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_RD_LVL
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#define CONFIG_NR_DRAM_BANKS 8
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#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
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#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
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#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
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#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
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#define CONFIG_SYS_MONITOR_BASE 0x00000000
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/* FLASH and environment organization */
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#define CONFIG_SYS_NO_FLASH
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#undef CONFIG_CMD_IMLS
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#define CONFIG_IDENT_STRING " for SMDK5250"
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_SECURE_BL1_ONLY
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/* Secure FW size configuration */
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#ifdef CONFIG_SECURE_BL1_ONLY
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#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
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#else
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#define CONFIG_SEC_FW_SIZE 0
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#endif
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/* Configuration of BL1, BL2, ENV Blocks on mmc */
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#define CONFIG_RES_BLOCK_SIZE (512)
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#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
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#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
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#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
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#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
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#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
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#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
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/* U-boot copy size from boot Media to DRAM.*/
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#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
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#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
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#define OM_STAT (0x1f << 1)
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#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
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#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
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#define CONFIG_DOS_PARTITION
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#define CONFIG_IRAM_STACK 0x02050000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
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/* I2C */
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#define CONFIG_SYS_I2C_INIT_BOARD
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#define CONFIG_HARD_I2C
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#define CONFIG_CMD_I2C
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#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
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#define CONFIG_DRIVER_S3C24X0_I2C
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_MAX_I2C_NUM 8
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#define CONFIG_SYS_I2C_SLAVE 0x0
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#define CONFIG_I2C_EDID
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/* PMIC */
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#define CONFIG_PMIC
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#define CONFIG_PMIC_I2C
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#define CONFIG_PMIC_MAX77686
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/* SPI */
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_SPI_FLASH
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#ifdef CONFIG_SPI_FLASH
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#define CONFIG_EXYNOS_SPI
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_SPI
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#define CONFIG_SPI_FLASH_WINBOND
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#define CONFIG_SF_DEFAULT_SPEED 50000000
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#define EXYNOS5_SPI_NUM_CONTROLLERS 5
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#endif
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#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SPI_MODE SPI_MODE_0
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#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
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#define CONFIG_ENV_SPI_BUS 1
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#define CONFIG_ENV_SPI_MAX_HZ 50000000
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#endif
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/* PMIC */
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#define CONFIG_POWER
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#define CONFIG_POWER_I2C
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#define CONFIG_POWER_MAX77686
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/* SPI */
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_SPI_FLASH
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#ifdef CONFIG_SPI_FLASH
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#define CONFIG_EXYNOS_SPI
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_SPI
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#define CONFIG_SPI_FLASH_WINBOND
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#define CONFIG_SF_DEFAULT_SPEED 50000000
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#define EXYNOS5_SPI_NUM_CONTROLLERS 5
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#endif
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#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SPI_MODE SPI_MODE_0
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#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
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#define CONFIG_ENV_SPI_BUS 1
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#define CONFIG_ENV_SPI_MAX_HZ 50000000
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#endif
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/* Ethernet Controllor Driver */
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#ifdef CONFIG_CMD_NET
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#define CONFIG_SMC911X
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#define CONFIG_SMC911X_BASE 0x5000000
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#define CONFIG_SMC911X_16_BIT
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#define CONFIG_ENV_SROM_BANK 1
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#endif /*CONFIG_CMD_NET*/
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/* Enable PXE Support */
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#ifdef CONFIG_CMD_NET
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#define CONFIG_CMD_PXE
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#define CONFIG_MENU
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#endif
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/* Sound */
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#define CONFIG_CMD_SOUND
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#ifdef CONFIG_CMD_SOUND
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#define CONFIG_SOUND
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#define CONFIG_I2S
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#define CONFIG_SOUND_WM8994
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#endif
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/* Enable devicetree support */
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#define CONFIG_OF_LIBFDT
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/* SHA hashing */
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#define CONFIG_CMD_HASH
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#define CONFIG_HASH_VERIFY
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#define CONFIG_SHA1
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#define CONFIG_SHA256
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#endif /* __CONFIG_H */
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