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cb3ce95401
In order to make it easier to move on to dropping common.h from code directly, remove common.h inclusion from the rest of the header file which had been including it. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
310 lines
11 KiB
C
310 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Cadence PCIe controlloer definitions
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* Adapted from linux kernel driver.
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* Copyright (c) 2017 Cadence
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*
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* Copyright (c) 2019
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* Written by Ramon Fried <ramon.fried@gmail.com>
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*/
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#ifndef PCIE_CADENCE_H
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#define PCIE_CADENCE_H
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#include <pci_ep.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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/*
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* Local Management Registers
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*/
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#define CDNS_PCIE_LM_BASE 0x00100000
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/* Vendor ID Register */
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#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044)
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#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0)
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#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0
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#define CDNS_PCIE_LM_ID_VENDOR(vid) \
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(((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK)
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#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16)
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#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16
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#define CDNS_PCIE_LM_ID_SUBSYS(sub) \
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(((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK)
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/* Root Port Requestor ID Register */
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#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228)
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#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0)
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#define CDNS_PCIE_LM_RP_RID_SHIFT 0
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#define CDNS_PCIE_LM_RP_RID_(rid) \
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(((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK)
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/* Endpoint Bus and Device Number Register */
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#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c)
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#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0)
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#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0
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#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8)
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#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8
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/* Endpoint Function f BAR b Configuration Registers */
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#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \
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(CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008)
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#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \
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(CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008)
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#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \
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(GENMASK(4, 0) << ((b) * 8))
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#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \
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(((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b))
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#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \
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(GENMASK(7, 5) << ((b) * 8))
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#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \
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(((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))
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/* Endpoint Function Configuration Register */
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#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0)
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/* Root Complex BAR Configuration Register */
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#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300)
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#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0)
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#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \
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(((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK)
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#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6)
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#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \
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(((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK)
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#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9)
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#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \
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(((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK)
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#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14)
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#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \
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(((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK)
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#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17)
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#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0
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#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18)
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#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19)
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#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0
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#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20)
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#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31)
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/* BAR control values applicable to both Endpoint Function and Root Complex */
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#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0
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#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1
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#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4
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#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5
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#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6
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#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7
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/*
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* Endpoint Function Registers (PCI configuration space for endpoint functions)
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*/
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#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12))
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#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90
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/*
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* Root Port Registers (PCI configuration space for the root port function)
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*/
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#define CDNS_PCIE_RP_BASE 0x00200000
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/*
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* Address Translation Registers
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*/
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#define CDNS_PCIE_AT_BASE 0x00400000
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/* Region r Outbound AXI to PCIe Address Translation Register 0 */
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#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \
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(CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020)
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#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)
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#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \
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(((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
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#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12)
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#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
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(((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK)
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#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20)
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#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
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(((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)
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/* Region r Outbound AXI to PCIe Address Translation Register 1 */
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#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \
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(CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020)
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/* Region r Outbound PCIe Descriptor Register 0 */
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#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \
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(CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020)
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#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0)
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#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2
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#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6
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#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa
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#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb
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#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc
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#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd
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/* Bit 23 MUST be set in RC mode. */
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#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23)
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#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24)
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#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \
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(((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK)
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/* Region r Outbound PCIe Descriptor Register 1 */
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#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \
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(CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020)
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#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0)
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#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \
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((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK)
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/* Region r AXI Region Base Address Register 0 */
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#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \
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(CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020)
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#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0)
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#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \
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(((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
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/* Region r AXI Region Base Address Register 1 */
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#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \
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(CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020)
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/* Root Port BAR Inbound PCIe to AXI Address Translation Register */
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#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \
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(CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008)
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#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0)
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#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \
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(((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
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#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
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(CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
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/* AXI link down register */
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#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824)
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enum cdns_pcie_rp_bar {
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RP_BAR0,
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RP_BAR1,
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RP_NO_BAR
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};
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/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
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#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \
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(CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008)
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#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \
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(CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008)
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/* Normal/Vendor specific message access: offset inside some outbound region */
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#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5)
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#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \
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(((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK)
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#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8)
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#define CDNS_PCIE_NORMAL_MSG_CODE(code) \
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(((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK)
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#define CDNS_PCIE_MSG_NO_DATA BIT(16)
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#define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */
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enum cdns_pcie_msg_code {
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MSG_CODE_ASSERT_INTA = 0x20,
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MSG_CODE_ASSERT_INTB = 0x21,
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MSG_CODE_ASSERT_INTC = 0x22,
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MSG_CODE_ASSERT_INTD = 0x23,
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MSG_CODE_DEASSERT_INTA = 0x24,
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MSG_CODE_DEASSERT_INTB = 0x25,
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MSG_CODE_DEASSERT_INTC = 0x26,
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MSG_CODE_DEASSERT_INTD = 0x27,
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};
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enum cdns_pcie_msg_routing {
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/* Route to Root Complex */
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MSG_ROUTING_TO_RC,
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/* Use Address Routing */
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MSG_ROUTING_BY_ADDR,
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/* Use ID Routing */
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MSG_ROUTING_BY_ID,
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/* Route as Broadcast Message from Root Complex */
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MSG_ROUTING_BCAST,
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/* Local message; terminate at receiver (INTx messages) */
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MSG_ROUTING_LOCAL,
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/* Gather & route to Root Complex (PME_TO_Ack message) */
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MSG_ROUTING_GATHER,
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};
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struct cdns_pcie {
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void __iomem *reg_base;
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u32 max_functions;
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u32 max_regions;
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};
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/* Register access */
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static inline void cdns_pcie_writeb(struct cdns_pcie *pcie, u32 reg, u8 value)
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{
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writeb(value, pcie->reg_base + reg);
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}
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static inline void cdns_pcie_writew(struct cdns_pcie *pcie, u32 reg, u16 value)
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{
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writew(value, pcie->reg_base + reg);
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}
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static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value)
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{
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writel(value, pcie->reg_base + reg);
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}
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static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg)
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{
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return readl(pcie->reg_base + reg);
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}
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/* Root Port register access */
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static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie,
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u32 reg, u8 value)
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{
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writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
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}
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static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie,
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u32 reg, u16 value)
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{
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writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
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}
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static inline void cdns_pcie_rp_writel(struct cdns_pcie *pcie,
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u32 reg, u32 value)
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{
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writel(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
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}
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/* Endpoint Function register access */
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static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn,
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u32 reg, u8 value)
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{
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writeb(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
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}
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static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn,
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u32 reg, u16 value)
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{
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writew(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
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}
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static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn,
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u32 reg, u32 value)
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{
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writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
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}
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static inline u8 cdns_pcie_ep_fn_readb(struct cdns_pcie *pcie, u8 fn, u32 reg)
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{
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return readb(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
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}
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static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg)
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{
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return readw(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
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}
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static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg)
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{
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return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
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}
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#endif /* end of include guard: PCIE_CADENCE_H */
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