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62534beb2f
405 SDRAM: - The SDRAM parameters can now be defined in the board
config file and the 405 SDRAM controller values will
be calculated upon bootup (see PPChameleonEVB).
When those settings are not defined in the board
config file, the register setup will be as it is now,
so this implementation should not break any current
design using this code.
Thanks to Andrea Marson from DAVE for this patch.
440 DDR: - Added function sdram_tr1_set to auto calculate the
TR1 value for the DDR.
- Added ECC support (see p3p440).
Patch by Stefan Roese, 17 Mar 2006
832 lines
28 KiB
C
832 lines
28 KiB
C
/*
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* (C) Copyright 2003-2005
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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*
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* (C) Copyright 2003
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* DAVE Srl
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*
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* http://www.dave-tech.it
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* http://www.wawnet.biz
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* mailto:info@wawnet.biz
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*
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* Credits: Stefan Roese, Wolfgang Denk
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
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#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
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#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
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#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
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#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
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#endif
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/* Only one of the following two symbols must be defined (default is 25 MHz)
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* CONFIG_PPCHAMELEON_CLK_25
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* CONFIG_PPCHAMELEON_CLK_33
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*/
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#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
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#define CONFIG_PPCHAMELEON_CLK_25
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#endif
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#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
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#error "* Two external frequencies (SysClk) are defined! *"
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#endif
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#undef CONFIG_PPCHAMELEON_SMI712
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/*
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* Debug stuff
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*/
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#undef __DEBUG_START_FROM_SRAM__
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#define __DISABLE_MACHINE_EXCEPTION__
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#ifdef __DEBUG_START_FROM_SRAM__
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#define CFG_DUMMY_FLASH_SIZE 1024*1024*4
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#endif
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_405EP 1 /* This is a PPC405 CPU */
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#define CONFIG_4xx 1 /* ...member of PPC4xx family */
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#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
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#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
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#ifdef CONFIG_PPCHAMELEON_CLK_25
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# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
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#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
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# define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
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#else
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# error "* External frequency (SysClk) not defined! *"
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#endif
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#undef CONFIG_BOOTARGS
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/* Ethernet stuff */
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#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
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#define CONFIG_ETHADDR 00:50:c2:1e:af:fe
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#define CONFIG_HAS_ETH1
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#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#undef CONFIG_EXT_PHY
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#define CONFIG_NET_MULTI 1
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#define CONFIG_MII 1 /* MII PHY management */
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#ifndef CONFIG_EXT_PHY
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#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
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#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
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#else
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#define CONFIG_PHY_ADDR 2 /* PHY address */
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#endif
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#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_ELF | \
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CFG_CMD_EEPROM | \
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CFG_CMD_I2C | \
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CFG_CMD_IRQ | \
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CFG_CMD_JFFS2 | \
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CFG_CMD_MII | \
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CFG_CMD_NAND | \
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CFG_CMD_NFS | \
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CFG_CMD_PCI | \
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CFG_CMD_SNTP )
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */
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#define CFG_I2C_RTC_ADDR 0x68
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#define CFG_M41T11_BASE_YEAR 1900
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/*
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* SDRAM configuration (please see cpu/ppc/sdram.[ch])
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*/
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#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
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/* SDRAM timings used in datasheet */
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#define CFG_SDRAM_CL 2
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#define CFG_SDRAM_tRP 20
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#define CFG_SDRAM_tRC 65
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#define CFG_SDRAM_tRCD 20
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#undef CFG_SDRAM_tRFC
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#undef CFG_HUSH_PARSER /* use "hush" command parser */
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
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#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
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#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
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#define CFG_BASE_BAUD 691200
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/* The following table includes the supported baudrates */
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#define CFG_BAUDRATE_TABLE \
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
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57600, 115200, 230400, 460800, 921600 }
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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/*-----------------------------------------------------------------------
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* NAND-FLASH stuff
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*-----------------------------------------------------------------------
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*/
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/*
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* nand device 1 on dave (PPChameleonEVB) needs more time,
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* so we just introduce additional wait in nand_wait(),
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* effectively for both devices.
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*/
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#define PPCHAMELON_NAND_TIMER_HACK
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#define CFG_NAND0_BASE 0xFF400000
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#define CFG_NAND1_BASE 0xFF000000
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#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, CFG_NAND1_BASE }
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#define NAND_BIG_DELAY_US 25
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#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
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#define NAND_MAX_CHIPS 1
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#define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
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#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
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#define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
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#define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
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#define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
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#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
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#define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
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#define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
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#define MACRO_NAND_DISABLE_CE(nandptr) do \
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{ \
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switch((unsigned long)nandptr) \
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{ \
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case CFG_NAND0_BASE: \
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
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break; \
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case CFG_NAND1_BASE: \
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
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break; \
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} \
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} while(0)
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#define MACRO_NAND_ENABLE_CE(nandptr) do \
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{ \
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switch((unsigned long)nandptr) \
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{ \
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case CFG_NAND0_BASE: \
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
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break; \
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case CFG_NAND1_BASE: \
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
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break; \
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} \
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} while(0)
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#define MACRO_NAND_CTL_CLRALE(nandptr) do \
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{ \
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switch((unsigned long)nandptr) \
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{ \
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case CFG_NAND0_BASE: \
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
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break; \
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case CFG_NAND1_BASE: \
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
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break; \
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} \
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} while(0)
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#define MACRO_NAND_CTL_SETALE(nandptr) do \
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{ \
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switch((unsigned long)nandptr) \
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{ \
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case CFG_NAND0_BASE: \
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
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break; \
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case CFG_NAND1_BASE: \
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
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break; \
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} \
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} while(0)
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#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
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{ \
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switch((unsigned long)nandptr) \
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{ \
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case CFG_NAND0_BASE: \
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
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break; \
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case CFG_NAND1_BASE: \
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
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break; \
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} \
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} while(0)
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#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
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switch((unsigned long)nandptr) { \
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case CFG_NAND0_BASE: \
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
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break; \
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case CFG_NAND1_BASE: \
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
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break; \
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} \
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} while(0)
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#if 0
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#define SECTORSIZE 512
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#define NAND_NO_RB
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define NAND_ChipID_UNKNOWN 0x00
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#define NAND_MAX_FLOORS 1
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#ifdef NAND_NO_RB
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/* constant delay (see also tR in the datasheet) */
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#define NAND_WAIT_READY(nand) do { \
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udelay(12); \
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} while (0)
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#else
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/* use the R/B pin */
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/* TBD */
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#endif
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#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
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#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
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#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
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#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
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#endif
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#undef CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
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#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
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#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
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#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
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#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
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#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
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#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
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#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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/* Reserve 256 kB for Monitor */
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/*
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#define CFG_FLASH_BASE 0xFFFC0000
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MONITOR_LEN (256 * 1024)
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*/
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/* Reserve 320 kB for Monitor */
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#define CFG_FLASH_BASE 0xFFFB0000
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MONITOR_LEN (320 * 1024)
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
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#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
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#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
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/*
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* The following defines are added for buggy IOP480 byte interface.
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* All other boards should use the standard values (CPCI405 etc.)
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*/
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#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
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#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
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#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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/*-----------------------------------------------------------------------
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* Environment Variable setup
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*/
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#ifdef ENVIRONMENT_IN_EEPROM
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#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
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#define CFG_ENV_SIZE 0x700 /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/
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#else /* DEFAULT: environment in flash, using redundand flash sectors */
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#define CFG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
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#define CFG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
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#define CFG_ENV_ADDR_REDUND 0xFFFFA000
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#define CFG_ENV_SIZE_REDUND 0x2000
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#endif /* ENVIRONMENT_IN_EEPROM */
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#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
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#define CFG_NVRAM_SIZE 242 /* NVRAM size */
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/*-----------------------------------------------------------------------
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* I2C EEPROM (CAT24WC16) for environment
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*/
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#define CONFIG_HARD_I2C /* I2c with hardware support */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
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#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
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#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
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/* 16 byte page write mode using*/
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/* last 4 bits of the address */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
|
#define CFG_EEPROM_PAGE_WRITE_ENABLE
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* Cache Configuration
|
|
*/
|
|
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
|
|
/* have only 8kB, 16kB is save here */
|
|
#define CFG_CACHELINE_SIZE 32 /* ... */
|
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
|
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
|
#endif
|
|
|
|
/*
|
|
* Init Memory Controller:
|
|
*
|
|
* BR0/1 and OR0/1 (FLASH)
|
|
*/
|
|
|
|
#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* External Bus Controller (EBC) Setup
|
|
*/
|
|
|
|
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
|
|
#define CFG_EBC_PB0AP 0x92015480
|
|
#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
|
|
|
|
/* Memory Bank 1 (External SRAM) initialization */
|
|
/* Since this must replace NOR Flash, we use the same settings for CS0 */
|
|
#define CFG_EBC_PB1AP 0x92015480
|
|
#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
|
|
|
|
/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
|
|
#define CFG_EBC_PB2AP 0x92015480
|
|
#define CFG_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
|
|
|
|
/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
|
|
#define CFG_EBC_PB3AP 0x92015480
|
|
#define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
|
|
|
|
#ifdef CONFIG_PPCHAMELEON_SMI712
|
|
/*
|
|
* Video console (graphic: SMI LynxEM)
|
|
*/
|
|
#define CONFIG_VIDEO
|
|
#define CONFIG_CFB_CONSOLE
|
|
#define CONFIG_VIDEO_SMI_LYNXEM
|
|
#define CONFIG_VIDEO_LOGO
|
|
/*#define CONFIG_VIDEO_BMP_LOGO*/
|
|
#define CONFIG_CONSOLE_EXTRA_INFO
|
|
#define CONFIG_VGA_AS_SINGLE_DEVICE
|
|
/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
|
|
#define CFG_ISA_IO 0xE8000000
|
|
/* see also drivers/videomodes.c */
|
|
#define CFG_DEFAULT_VIDEO_MODE 0x303
|
|
#endif
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* FPGA stuff
|
|
*/
|
|
/* FPGA internal regs */
|
|
#define CFG_FPGA_MODE 0x00
|
|
#define CFG_FPGA_STATUS 0x02
|
|
#define CFG_FPGA_TS 0x04
|
|
#define CFG_FPGA_TS_LOW 0x06
|
|
#define CFG_FPGA_TS_CAP0 0x10
|
|
#define CFG_FPGA_TS_CAP0_LOW 0x12
|
|
#define CFG_FPGA_TS_CAP1 0x14
|
|
#define CFG_FPGA_TS_CAP1_LOW 0x16
|
|
#define CFG_FPGA_TS_CAP2 0x18
|
|
#define CFG_FPGA_TS_CAP2_LOW 0x1a
|
|
#define CFG_FPGA_TS_CAP3 0x1c
|
|
#define CFG_FPGA_TS_CAP3_LOW 0x1e
|
|
|
|
/* FPGA Mode Reg */
|
|
#define CFG_FPGA_MODE_CF_RESET 0x0001
|
|
#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
|
|
#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
|
|
#define CFG_FPGA_MODE_TS_CLEAR 0x2000
|
|
|
|
/* FPGA Status Reg */
|
|
#define CFG_FPGA_STATUS_DIP0 0x0001
|
|
#define CFG_FPGA_STATUS_DIP1 0x0002
|
|
#define CFG_FPGA_STATUS_DIP2 0x0004
|
|
#define CFG_FPGA_STATUS_FLASH 0x0008
|
|
#define CFG_FPGA_STATUS_TS_IRQ 0x1000
|
|
|
|
#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
|
|
#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
|
|
|
|
/* FPGA program pin configuration */
|
|
#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
|
|
#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
|
|
#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
|
|
#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
|
|
#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* Definitions for initial stack pointer and data area (in data cache)
|
|
*/
|
|
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
|
|
#define CFG_TEMP_STACK_OCM 1
|
|
|
|
/* On Chip Memory location */
|
|
#define CFG_OCM_DATA_ADDR 0xF8000000
|
|
#define CFG_OCM_DATA_SIZE 0x1000
|
|
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
|
|
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
|
|
|
|
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
|
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
|
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* Definitions for GPIO setup (PPC405EP specific)
|
|
*
|
|
* GPIO0[0] - External Bus Controller BLAST output
|
|
* GPIO0[1-9] - Instruction trace outputs -> GPIO
|
|
* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
|
|
* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
|
|
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
|
|
* GPIO0[24-27] - UART0 control signal inputs/outputs
|
|
* GPIO0[28-29] - UART1 data signal input/output
|
|
* GPIO0[30] - EMAC0 input
|
|
* GPIO0[31] - EMAC1 reject packet as output
|
|
*/
|
|
#define CFG_GPIO0_OSRH 0x40000550
|
|
#define CFG_GPIO0_OSRL 0x00000110
|
|
#define CFG_GPIO0_ISR1H 0x00000000
|
|
/*#define CFG_GPIO0_ISR1L 0x15555445*/
|
|
#define CFG_GPIO0_ISR1L 0x15555444
|
|
#define CFG_GPIO0_TSRH 0x00000000
|
|
#define CFG_GPIO0_TSRL 0x00000000
|
|
#define CFG_GPIO0_TCR 0xF7FF8014
|
|
|
|
/*
|
|
* Internal Definitions
|
|
*
|
|
* Boot Flags
|
|
*/
|
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
|
|
|
|
|
#define CONFIG_NO_SERIAL_EEPROM
|
|
|
|
/*--------------------------------------------------------------------*/
|
|
|
|
#ifdef CONFIG_NO_SERIAL_EEPROM
|
|
|
|
/*
|
|
!-----------------------------------------------------------------------
|
|
! Defines for entry options.
|
|
! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
|
|
! are plugged in the board will be utilized as non-ECC DIMMs.
|
|
!-----------------------------------------------------------------------
|
|
*/
|
|
#undef AUTO_MEMORY_CONFIG
|
|
#define DIMM_READ_ADDR 0xAB
|
|
#define DIMM_WRITE_ADDR 0xAA
|
|
|
|
#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
|
|
#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
|
|
#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
|
|
#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */
|
|
#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
|
|
#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
|
|
#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
|
|
#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
|
|
#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
|
|
#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
|
|
|
|
/* Defines for CPC0_PLLMR1 Register fields */
|
|
#define PLL_ACTIVE 0x80000000
|
|
#define CPC0_PLLMR1_SSCS 0x80000000
|
|
#define PLL_RESET 0x40000000
|
|
#define CPC0_PLLMR1_PLLR 0x40000000
|
|
/* Feedback multiplier */
|
|
#define PLL_FBKDIV 0x00F00000
|
|
#define CPC0_PLLMR1_FBDV 0x00F00000
|
|
#define PLL_FBKDIV_16 0x00000000
|
|
#define PLL_FBKDIV_1 0x00100000
|
|
#define PLL_FBKDIV_2 0x00200000
|
|
#define PLL_FBKDIV_3 0x00300000
|
|
#define PLL_FBKDIV_4 0x00400000
|
|
#define PLL_FBKDIV_5 0x00500000
|
|
#define PLL_FBKDIV_6 0x00600000
|
|
#define PLL_FBKDIV_7 0x00700000
|
|
#define PLL_FBKDIV_8 0x00800000
|
|
#define PLL_FBKDIV_9 0x00900000
|
|
#define PLL_FBKDIV_10 0x00A00000
|
|
#define PLL_FBKDIV_11 0x00B00000
|
|
#define PLL_FBKDIV_12 0x00C00000
|
|
#define PLL_FBKDIV_13 0x00D00000
|
|
#define PLL_FBKDIV_14 0x00E00000
|
|
#define PLL_FBKDIV_15 0x00F00000
|
|
/* Forward A divisor */
|
|
#define PLL_FWDDIVA 0x00070000
|
|
#define CPC0_PLLMR1_FWDVA 0x00070000
|
|
#define PLL_FWDDIVA_8 0x00000000
|
|
#define PLL_FWDDIVA_7 0x00010000
|
|
#define PLL_FWDDIVA_6 0x00020000
|
|
#define PLL_FWDDIVA_5 0x00030000
|
|
#define PLL_FWDDIVA_4 0x00040000
|
|
#define PLL_FWDDIVA_3 0x00050000
|
|
#define PLL_FWDDIVA_2 0x00060000
|
|
#define PLL_FWDDIVA_1 0x00070000
|
|
/* Forward B divisor */
|
|
#define PLL_FWDDIVB 0x00007000
|
|
#define CPC0_PLLMR1_FWDVB 0x00007000
|
|
#define PLL_FWDDIVB_8 0x00000000
|
|
#define PLL_FWDDIVB_7 0x00001000
|
|
#define PLL_FWDDIVB_6 0x00002000
|
|
#define PLL_FWDDIVB_5 0x00003000
|
|
#define PLL_FWDDIVB_4 0x00004000
|
|
#define PLL_FWDDIVB_3 0x00005000
|
|
#define PLL_FWDDIVB_2 0x00006000
|
|
#define PLL_FWDDIVB_1 0x00007000
|
|
/* PLL tune bits */
|
|
#define PLL_TUNE_MASK 0x000003FF
|
|
#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
|
|
#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
|
|
#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
|
|
#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
|
|
#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
|
|
#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
|
|
#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
|
|
|
|
/* Defines for CPC0_PLLMR0 Register fields */
|
|
/* CPU divisor */
|
|
#define PLL_CPUDIV 0x00300000
|
|
#define CPC0_PLLMR0_CCDV 0x00300000
|
|
#define PLL_CPUDIV_1 0x00000000
|
|
#define PLL_CPUDIV_2 0x00100000
|
|
#define PLL_CPUDIV_3 0x00200000
|
|
#define PLL_CPUDIV_4 0x00300000
|
|
/* PLB divisor */
|
|
#define PLL_PLBDIV 0x00030000
|
|
#define CPC0_PLLMR0_CBDV 0x00030000
|
|
#define PLL_PLBDIV_1 0x00000000
|
|
#define PLL_PLBDIV_2 0x00010000
|
|
#define PLL_PLBDIV_3 0x00020000
|
|
#define PLL_PLBDIV_4 0x00030000
|
|
/* OPB divisor */
|
|
#define PLL_OPBDIV 0x00003000
|
|
#define CPC0_PLLMR0_OPDV 0x00003000
|
|
#define PLL_OPBDIV_1 0x00000000
|
|
#define PLL_OPBDIV_2 0x00001000
|
|
#define PLL_OPBDIV_3 0x00002000
|
|
#define PLL_OPBDIV_4 0x00003000
|
|
/* EBC divisor */
|
|
#define PLL_EXTBUSDIV 0x00000300
|
|
#define CPC0_PLLMR0_EPDV 0x00000300
|
|
#define PLL_EXTBUSDIV_2 0x00000000
|
|
#define PLL_EXTBUSDIV_3 0x00000100
|
|
#define PLL_EXTBUSDIV_4 0x00000200
|
|
#define PLL_EXTBUSDIV_5 0x00000300
|
|
/* MAL divisor */
|
|
#define PLL_MALDIV 0x00000030
|
|
#define CPC0_PLLMR0_MPDV 0x00000030
|
|
#define PLL_MALDIV_1 0x00000000
|
|
#define PLL_MALDIV_2 0x00000010
|
|
#define PLL_MALDIV_3 0x00000020
|
|
#define PLL_MALDIV_4 0x00000030
|
|
/* PCI divisor */
|
|
#define PLL_PCIDIV 0x00000003
|
|
#define CPC0_PLLMR0_PPFD 0x00000003
|
|
#define PLL_PCIDIV_1 0x00000000
|
|
#define PLL_PCIDIV_2 0x00000001
|
|
#define PLL_PCIDIV_3 0x00000002
|
|
#define PLL_PCIDIV_4 0x00000003
|
|
|
|
#ifdef CONFIG_PPCHAMELEON_CLK_25
|
|
/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
|
|
#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
|
|
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
|
|
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
|
#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
|
|
PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
|
|
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
|
|
|
#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
|
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
|
|
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
|
#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
|
|
PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
|
|
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
|
|
|
#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
|
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
|
|
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
|
#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
|
|
PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
|
|
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
|
|
|
#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
|
|
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
|
|
PLL_MALDIV_1 | PLL_PCIDIV_2)
|
|
#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
|
|
PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
|
|
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
|
|
|
|
#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
|
|
|
|
/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
|
|
#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
|
|
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
|
|
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
|
#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
|
|
PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
|
|
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
|
|
|
#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
|
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
|
|
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
|
#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
|
|
PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
|
|
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
|
|
|
#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
|
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
|
|
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
|
#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
|
|
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
|
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
|
|
|
#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
|
|
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
|
|
PLL_MALDIV_1 | PLL_PCIDIV_2)
|
|
#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
|
|
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
|
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
|
|
|
|
#else
|
|
#error "* External frequency (SysClk) not defined! *"
|
|
#endif
|
|
|
|
#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
|
|
/* Model HI */
|
|
#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
|
|
#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
|
|
#define CFG_OPB_FREQ 55555555
|
|
/* Model ME */
|
|
#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
|
|
#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
|
|
#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
|
|
#define CFG_OPB_FREQ 66666666
|
|
#else
|
|
/* Model BA (default) */
|
|
#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
|
|
#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
|
|
#define CFG_OPB_FREQ 66666666
|
|
#endif
|
|
|
|
#endif /* CONFIG_NO_SERIAL_EEPROM */
|
|
|
|
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
|
|
#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
|
|
|
|
/*
|
|
* JFFS2 partitions
|
|
*/
|
|
|
|
/* No command line, one static partition */
|
|
#undef CONFIG_JFFS2_CMDLINE
|
|
#define CONFIG_JFFS2_DEV "nand0"
|
|
#define CONFIG_JFFS2_PART_SIZE 0x00400000
|
|
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
|
|
|
|
/* mtdparts command line support */
|
|
/*
|
|
#define CONFIG_JFFS2_CMDLINE
|
|
#define MTDIDS_DEFAULT "nor0=PPChameleon-0,nand0=ppchameleonevb-nand"
|
|
*/
|
|
|
|
/* 256 kB U-boot image */
|
|
/*
|
|
#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
|
|
"1792k(user),256k(u-boot);" \
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"ppchameleonevb-nand:-(nand)"
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*/
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/* 320 kB U-boot image */
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/*
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#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
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"1728k(user),320k(u-boot);" \
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"ppchameleonevb-nand:-(nand)"
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|
*/
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|
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#endif /* __CONFIG_H */
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