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5c952cf024
- Add support for Altera Nios-II processors. - Add support for Psyent PCI-5441 board. - Add support for Psyent PK1C20 board.
156 lines
6.7 KiB
C
156 lines
6.7 KiB
C
/*
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*------------------------------------------------------------------------
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* BOARD/CPU
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*----------------------------------------------------------------------*/
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#define CONFIG_PCI5441 1 /* PCI-5441 board */
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#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
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#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */
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#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
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#define CFG_NIOS_SYSID_BASE 0x00920828 /* System id address */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
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/*------------------------------------------------------------------------
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* CACHE -- the following will support II/s and II/f. The II/s does not
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* have dcache, so the cache instructions will behave as NOPs.
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*----------------------------------------------------------------------*/
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#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */
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#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */
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#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
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#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
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/*------------------------------------------------------------------------
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* MEMORY BASE ADDRESSES
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*----------------------------------------------------------------------*/
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#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */
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#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
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#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */
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#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */
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/*------------------------------------------------------------------------
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* MEMORY ORGANIZATION
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* -Monitor at top.
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* -The heap is placed below the monitor.
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* -Global data is placed below the heap.
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* -The stack is placed below global data (&grows down).
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*----------------------------------------------------------------------*/
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#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128k */
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#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
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#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP CFG_GBL_DATA_OFFSET
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/*------------------------------------------------------------------------
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* FLASH (AM29LV065D)
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*----------------------------------------------------------------------*/
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#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
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#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
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#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
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#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
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#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */
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/*------------------------------------------------------------------------
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* ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
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* CFG_RESET_ADDR, since we assume the monitor is stored at the
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* reset address, no? This will keep the environment in user region
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* of flash. NOTE: the monitor length must be multiple of sector size
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* (which is common practice).
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*----------------------------------------------------------------------*/
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#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */
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#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
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#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
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#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN)
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/*------------------------------------------------------------------------
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* CONSOLE
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*----------------------------------------------------------------------*/
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#if defined(CONFIG_CONSOLE_JTAG)
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#define CFG_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */
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#else
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#define CFG_NIOS_CONSOLE 0x009208a0 /* UART base addr */
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#endif
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#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
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#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
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#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
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#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
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/*------------------------------------------------------------------------
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* DEBUG
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*----------------------------------------------------------------------*/
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#undef CONFIG_ROM_STUBS /* Stubs not in ROM */
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/*------------------------------------------------------------------------
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* TIMEBASE --
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*
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* The high res timer defaults to 1 msec. Since it includes the period
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* registers, we can slow it down to 10 msec using TMRCNT. If the default
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* period is acceptable, TMRCNT can be left undefined.
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*----------------------------------------------------------------------*/
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#define CFG_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */
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#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */
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#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */
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#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
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#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
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/*------------------------------------------------------------------------
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* COMMANDS
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*----------------------------------------------------------------------*/
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#define CONFIG_COMMANDS (CFG_CMD_BDI | \
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CFG_CMD_ECHO | \
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CFG_CMD_ENV | \
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CFG_CMD_FLASH | \
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CFG_CMD_IMI | \
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CFG_CMD_IRQ | \
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CFG_CMD_LOADS | \
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CFG_CMD_LOADB | \
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CFG_CMD_MEMORY | \
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CFG_CMD_MISC | \
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CFG_CMD_RUN | \
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CFG_CMD_SAVES )
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#include <cmd_confdefs.h>
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/*------------------------------------------------------------------------
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* MISC
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*----------------------------------------------------------------------*/
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#define CFG_LONGHELP /* Provide extended help*/
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#define CFG_PROMPT "==> " /* Command prompt */
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#define CFG_CBSIZE 256 /* Console I/O buf size */
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#define CFG_MAXARGS 16 /* Max command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
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#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */
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#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */
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#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000
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#endif /* __CONFIG_H */
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