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056fbc73d5
This patch added support for accessing dual memories in parallel connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
309 lines
9.4 KiB
C
309 lines
9.4 KiB
C
/*
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* Common SPI Interface: Controller-specific definitions
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*
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* (C) Copyright 2001
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* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SPI_H_
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#define _SPI_H_
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/* SPI mode flags */
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#define SPI_CPHA 0x01 /* clock phase */
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#define SPI_CPOL 0x02 /* clock polarity */
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#define SPI_MODE_0 (0|0) /* (original MicroWire) */
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#define SPI_MODE_1 (0|SPI_CPHA)
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#define SPI_MODE_2 (SPI_CPOL|0)
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#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
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#define SPI_CS_HIGH 0x04 /* CS active high */
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#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
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#define SPI_3WIRE 0x10 /* SI/SO signals shared */
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#define SPI_LOOP 0x20 /* loopback mode */
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#define SPI_SLAVE 0x40 /* slave mode */
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#define SPI_PREAMBLE 0x80 /* Skip preamble bytes */
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/* SPI transfer flags */
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#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */
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#define SPI_XFER_END 0x02 /* Deassert CS after transfer */
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#define SPI_XFER_MMAP 0x08 /* Memory Mapped start */
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#define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */
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#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
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#define SPI_XFER_U_PAGE (1 << 5)
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/* SPI TX operation modes */
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#define SPI_OPM_TX_QPP 1 << 0
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/* SPI RX operation modes */
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#define SPI_OPM_RX_AS 1 << 0
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#define SPI_OPM_RX_DOUT 1 << 1
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#define SPI_OPM_RX_DIO 1 << 2
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#define SPI_OPM_RX_QOF 1 << 3
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#define SPI_OPM_RX_QIOF 1 << 4
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#define SPI_OPM_RX_EXTN SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \
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SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
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SPI_OPM_RX_QIOF
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/* SPI bus connection options */
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#define SPI_CONN_DUAL_SHARED 1 << 0
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#define SPI_CONN_DUAL_SEPARATED 1 << 1
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/* Header byte that marks the start of the message */
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#define SPI_PREAMBLE_END_BYTE 0xec
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#define SPI_DEFAULT_WORDLEN 8
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/**
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* struct spi_slave - Representation of a SPI slave
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*
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* Drivers are expected to extend this with controller-specific data.
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*
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* @bus: ID of the bus that the slave is attached to.
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* @cs: ID of the chip select connected to the slave.
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* @op_mode_rx: SPI RX operation mode.
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* @op_mode_tx: SPI TX operation mode.
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* @wordlen: Size of SPI word in number of bits
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* @max_write_size: If non-zero, the maximum number of bytes which can
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* be written at once, excluding command bytes.
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* @memory_map: Address of read-only SPI flash access.
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* @option: Varies SPI bus options - separate, shared bus.
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* @flags: Indication of SPI flags.
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*/
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struct spi_slave {
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unsigned int bus;
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unsigned int cs;
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u8 op_mode_rx;
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u8 op_mode_tx;
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unsigned int wordlen;
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unsigned int max_write_size;
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void *memory_map;
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u8 option;
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u8 flags;
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};
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/**
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* Initialization, must be called once on start up.
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*
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* TODO: I don't think we really need this.
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*/
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void spi_init(void);
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/**
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* spi_do_alloc_slave - Allocate a new SPI slave (internal)
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*
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* Allocate and zero all fields in the spi slave, and set the bus/chip
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* select. Use the helper macro spi_alloc_slave() to call this.
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*
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* @offset: Offset of struct spi_slave within slave structure.
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* @size: Size of slave structure.
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* @bus: Bus ID of the slave chip.
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* @cs: Chip select ID of the slave chip on the specified bus.
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*/
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void *spi_do_alloc_slave(int offset, int size, unsigned int bus,
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unsigned int cs);
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/**
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* spi_alloc_slave - Allocate a new SPI slave
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*
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* Allocate and zero all fields in the spi slave, and set the bus/chip
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* select.
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*
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* @_struct: Name of structure to allocate (e.g. struct tegra_spi).
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* This structure must contain a member 'struct spi_slave *slave'.
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* @bus: Bus ID of the slave chip.
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* @cs: Chip select ID of the slave chip on the specified bus.
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*/
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#define spi_alloc_slave(_struct, bus, cs) \
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spi_do_alloc_slave(offsetof(_struct, slave), \
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sizeof(_struct), bus, cs)
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/**
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* spi_alloc_slave_base - Allocate a new SPI slave with no private data
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*
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* Allocate and zero all fields in the spi slave, and set the bus/chip
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* select.
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*
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* @bus: Bus ID of the slave chip.
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* @cs: Chip select ID of the slave chip on the specified bus.
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*/
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#define spi_alloc_slave_base(bus, cs) \
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spi_do_alloc_slave(0, sizeof(struct spi_slave), bus, cs)
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/**
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* Set up communications parameters for a SPI slave.
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*
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* This must be called once for each slave. Note that this function
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* usually doesn't touch any actual hardware, it only initializes the
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* contents of spi_slave so that the hardware can be easily
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* initialized later.
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*
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* @bus: Bus ID of the slave chip.
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* @cs: Chip select ID of the slave chip on the specified bus.
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* @max_hz: Maximum SCK rate in Hz.
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* @mode: Clock polarity, clock phase and other parameters.
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*
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* Returns: A spi_slave reference that can be used in subsequent SPI
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* calls, or NULL if one or more of the parameters are not supported.
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*/
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode);
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/**
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* Free any memory associated with a SPI slave.
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*
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* @slave: The SPI slave
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*/
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void spi_free_slave(struct spi_slave *slave);
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/**
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* Claim the bus and prepare it for communication with a given slave.
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*
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* This must be called before doing any transfers with a SPI slave. It
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* will enable and initialize any SPI hardware as necessary, and make
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* sure that the SCK line is in the correct idle state. It is not
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* allowed to claim the same bus for several slaves without releasing
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* the bus in between.
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*
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* @slave: The SPI slave
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*
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* Returns: 0 if the bus was claimed successfully, or a negative value
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* if it wasn't.
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*/
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int spi_claim_bus(struct spi_slave *slave);
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/**
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* Release the SPI bus
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*
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* This must be called once for every call to spi_claim_bus() after
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* all transfers have finished. It may disable any SPI hardware as
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* appropriate.
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*
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* @slave: The SPI slave
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*/
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void spi_release_bus(struct spi_slave *slave);
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/**
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* Set the word length for SPI transactions
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*
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* Set the word length (number of bits per word) for SPI transactions.
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*
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* @slave: The SPI slave
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* @wordlen: The number of bits in a word
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*
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* Returns: 0 on success, -1 on failure.
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*/
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int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen);
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/**
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* SPI transfer
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*
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* This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
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* "bitlen" bits in the SPI MISO port. That's just the way SPI works.
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*
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* The source of the outgoing bits is the "dout" parameter and the
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* destination of the input bits is the "din" parameter. Note that "dout"
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* and "din" can point to the same memory location, in which case the
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* input data overwrites the output data (since both are buffered by
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* temporary variables, this is OK).
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*
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* spi_xfer() interface:
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* @slave: The SPI slave which will be sending/receiving the data.
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* @bitlen: How many bits to write and read.
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* @dout: Pointer to a string of bits to send out. The bits are
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* held in a byte array and are sent MSB first.
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* @din: Pointer to a string of bits that will be filled in.
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* @flags: A bitwise combination of SPI_XFER_* flags.
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*
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* Returns: 0 on success, not 0 on failure
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*/
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags);
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/**
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* Determine if a SPI chipselect is valid.
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* This function is provided by the board if the low-level SPI driver
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* needs it to determine if a given chipselect is actually valid.
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*
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* Returns: 1 if bus:cs identifies a valid chip on this board, 0
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* otherwise.
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*/
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int spi_cs_is_valid(unsigned int bus, unsigned int cs);
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/**
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* Activate a SPI chipselect.
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* This function is provided by the board code when using a driver
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* that can't control its chipselects automatically (e.g.
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* common/soft_spi.c). When called, it should activate the chip select
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* to the device identified by "slave".
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*/
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void spi_cs_activate(struct spi_slave *slave);
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/**
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* Deactivate a SPI chipselect.
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* This function is provided by the board code when using a driver
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* that can't control its chipselects automatically (e.g.
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* common/soft_spi.c). When called, it should deactivate the chip
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* select to the device identified by "slave".
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*/
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void spi_cs_deactivate(struct spi_slave *slave);
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/**
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* Set transfer speed.
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* This sets a new speed to be applied for next spi_xfer().
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* @slave: The SPI slave
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* @hz: The transfer speed
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*/
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void spi_set_speed(struct spi_slave *slave, uint hz);
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/**
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* Write 8 bits, then read 8 bits.
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* @slave: The SPI slave we're communicating with
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* @byte: Byte to be written
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*
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* Returns: The value that was read, or a negative value on error.
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*
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* TODO: This function probably shouldn't be inlined.
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*/
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static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte)
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{
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unsigned char dout[2];
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unsigned char din[2];
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int ret;
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dout[0] = byte;
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dout[1] = 0;
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ret = spi_xfer(slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
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return ret < 0 ? ret : din[1];
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}
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/**
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* Set up a SPI slave for a particular device tree node
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*
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* This calls spi_setup_slave() with the correct bus number. Call
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* spi_free_slave() to free it later.
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*
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* @param blob: Device tree blob
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* @param slave_node: Slave node to use
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* @param spi_node: SPI peripheral node to use
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* @return pointer to new spi_slave structure
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*/
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struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
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int spi_node);
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/**
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* spi_base_setup_slave_fdt() - helper function to set up a SPI slace
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*
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* This decodes SPI properties from the slave node to determine the
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* chip select and SPI parameters.
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*
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* @blob: Device tree blob
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* @busnum: Bus number to use
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* @node: Device tree node for the SPI bus
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*/
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struct spi_slave *spi_base_setup_slave_fdt(const void *blob, int busnum,
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int node);
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#endif /* _SPI_H_ */
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