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bf667d5f15
Replace custom driver macros by PCIE_ECAM_OFFSET() macro from pci.h Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
345 lines
8.8 KiB
C
345 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* https://spdx.org/licenses
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*/
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <log.h>
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#include <malloc.h>
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#include <pci.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <linux/ioport.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* This driver supports multiple types of operations / host bridges / busses:
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*
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* OTX_ECAM: Octeon TX & TX2 ECAM (Enhanced Configuration Access Mechanism)
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* Used to access the internal on-chip devices which are connected
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* to internal buses
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* OTX_PEM: Octeon TX PEM (PCI Express MAC)
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* Used to access the external (off-chip) PCI devices
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* OTX2_PEM: Octeon TX2 PEM (PCI Express MAC)
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* Used to access the external (off-chip) PCI devices
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*/
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enum {
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OTX_ECAM,
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OTX_PEM,
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OTX2_PEM,
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};
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/**
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* struct octeontx_pci - Driver private data
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* @type: Device type matched via compatible (e.g. OTX_ECAM etc)
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* @cfg: Config resource
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* @bus: Bus resource
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*/
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struct octeontx_pci {
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unsigned int type;
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struct resource cfg;
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struct resource bus;
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};
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static ulong readl_size(uintptr_t addr, enum pci_size_t size)
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{
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ulong val;
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switch (size) {
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case PCI_SIZE_8:
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val = readb(addr);
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break;
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case PCI_SIZE_16:
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val = readw(addr);
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break;
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case PCI_SIZE_32:
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val = readl(addr);
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break;
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default:
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printf("Invalid size\n");
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return -EINVAL;
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};
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return val;
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}
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static void writel_size(uintptr_t addr, enum pci_size_t size, ulong valuep)
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{
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switch (size) {
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case PCI_SIZE_8:
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writeb(valuep, addr);
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break;
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case PCI_SIZE_16:
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writew(valuep, addr);
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break;
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case PCI_SIZE_32:
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writel(valuep, addr);
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break;
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default:
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printf("Invalid size\n");
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};
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}
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static bool octeontx_bdf_invalid(pci_dev_t bdf)
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{
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if (PCI_BUS(bdf) == 1 && PCI_DEV(bdf) > 0)
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return true;
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return false;
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}
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static int octeontx_ecam_read_config(const struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus);
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struct pci_controller *hose = dev_get_uclass_priv(bus);
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uintptr_t address;
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address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + pcie->bus.start - hose->first_busno,
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PCI_DEV(bdf), PCI_FUNC(bdf), offset);
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*valuep = readl_size(pcie->cfg.start + address, size);
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debug("%02x.%02x.%02x: u%d %x -> %lx\n",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, *valuep);
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return 0;
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}
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static int octeontx_ecam_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus);
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struct pci_controller *hose = dev_get_uclass_priv(bus);
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uintptr_t address;
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address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + pcie->bus.start - hose->first_busno,
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PCI_DEV(bdf), PCI_FUNC(bdf), offset);
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writel_size(pcie->cfg.start + address, size, value);
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debug("%02x.%02x.%02x: u%d %x <- %lx\n",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, value);
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return 0;
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}
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static int octeontx_pem_read_config(const struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus);
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struct pci_controller *hose = dev_get_uclass_priv(bus);
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uintptr_t address;
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u8 hdrtype;
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u8 pri_bus = pcie->bus.start + 1 - hose->first_busno;
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u32 bus_offs = (pri_bus << 16) | (pri_bus << 8) | (pri_bus << 0);
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*valuep = pci_conv_32_to_size(~0UL, offset, size);
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if (octeontx_bdf_invalid(bdf))
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return -EPERM;
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address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + 1 - hose->first_busno,
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PCI_DEV(bdf), PCI_FUNC(bdf), 0) << 4;
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*valuep = readl_size(pcie->cfg.start + address + offset, size);
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hdrtype = readb(pcie->cfg.start + address + PCI_HEADER_TYPE);
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if (hdrtype == PCI_HEADER_TYPE_BRIDGE &&
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offset >= PCI_PRIMARY_BUS &&
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offset <= PCI_SUBORDINATE_BUS &&
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*valuep != pci_conv_32_to_size(~0UL, offset, size))
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*valuep -= pci_conv_32_to_size(bus_offs, offset, size);
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return 0;
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}
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static int octeontx_pem_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus);
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struct pci_controller *hose = dev_get_uclass_priv(bus);
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uintptr_t address;
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u8 hdrtype;
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u8 pri_bus = pcie->bus.start + 1 - hose->first_busno;
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u32 bus_offs = (pri_bus << 16) | (pri_bus << 8) | (pri_bus << 0);
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address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + 1 - hose->first_busno,
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PCI_DEV(bdf), PCI_FUNC(bdf), 0) << 4;
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hdrtype = readb(pcie->cfg.start + address + PCI_HEADER_TYPE);
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if (hdrtype == PCI_HEADER_TYPE_BRIDGE &&
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offset >= PCI_PRIMARY_BUS &&
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offset <= PCI_SUBORDINATE_BUS &&
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value != pci_conv_32_to_size(~0UL, offset, size))
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value += pci_conv_32_to_size(bus_offs, offset, size);
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if (octeontx_bdf_invalid(bdf))
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return -EPERM;
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writel_size(pcie->cfg.start + address + offset, size, value);
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debug("%02x.%02x.%02x: u%d %x (%lx) <- %lx\n",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset,
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address, value);
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return 0;
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}
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static int octeontx2_pem_read_config(const struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus);
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struct pci_controller *hose = dev_get_uclass_priv(bus);
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uintptr_t address;
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*valuep = pci_conv_32_to_size(~0UL, offset, size);
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if (octeontx_bdf_invalid(bdf))
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return -EPERM;
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address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + 1 - hose->first_busno,
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PCI_DEV(bdf), PCI_FUNC(bdf), offset);
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*valuep = readl_size(pcie->cfg.start + address, size);
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debug("%02x.%02x.%02x: u%d %x (%lx) -> %lx\n",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset,
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address, *valuep);
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return 0;
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}
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static int octeontx2_pem_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus);
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struct pci_controller *hose = dev_get_uclass_priv(bus);
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uintptr_t address;
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if (octeontx_bdf_invalid(bdf))
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return -EPERM;
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address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + 1 - hose->first_busno,
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PCI_DEV(bdf), PCI_FUNC(bdf), offset);
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writel_size(pcie->cfg.start + address, size, value);
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debug("%02x.%02x.%02x: u%d %x (%lx) <- %lx\n",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset,
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address, value);
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return 0;
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}
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int pci_octeontx_read_config(const struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus);
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int ret = -EIO;
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switch (pcie->type) {
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case OTX_ECAM:
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ret = octeontx_ecam_read_config(bus, bdf, offset, valuep,
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size);
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break;
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case OTX_PEM:
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ret = octeontx_pem_read_config(bus, bdf, offset, valuep,
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size);
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break;
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case OTX2_PEM:
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ret = octeontx2_pem_read_config(bus, bdf, offset, valuep,
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size);
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break;
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}
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return ret;
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}
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int pci_octeontx_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus);
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int ret = -EIO;
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switch (pcie->type) {
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case OTX_ECAM:
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ret = octeontx_ecam_write_config(bus, bdf, offset, value,
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size);
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break;
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case OTX_PEM:
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ret = octeontx_pem_write_config(bus, bdf, offset, value,
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size);
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break;
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case OTX2_PEM:
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ret = octeontx2_pem_write_config(bus, bdf, offset, value,
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size);
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break;
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}
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return ret;
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}
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static int pci_octeontx_of_to_plat(struct udevice *dev)
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{
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return 0;
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}
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static int pci_octeontx_probe(struct udevice *dev)
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{
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struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(dev);
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int err;
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pcie->type = dev_get_driver_data(dev);
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err = dev_read_resource(dev, 0, &pcie->cfg);
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if (err) {
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debug("Error reading resource: %s\n", fdt_strerror(err));
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return err;
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}
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err = dev_read_pci_bus_range(dev, &pcie->bus);
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if (err) {
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debug("Error reading resource: %s\n", fdt_strerror(err));
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return err;
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}
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return 0;
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}
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static const struct dm_pci_ops pci_octeontx_ops = {
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.read_config = pci_octeontx_read_config,
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.write_config = pci_octeontx_write_config,
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};
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static const struct udevice_id pci_octeontx_ids[] = {
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{ .compatible = "cavium,pci-host-thunder-ecam", .data = OTX_ECAM },
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{ .compatible = "cavium,pci-host-octeontx-ecam", .data = OTX_ECAM },
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{ .compatible = "pci-host-ecam-generic", .data = OTX_ECAM },
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{ .compatible = "cavium,pci-host-thunder-pem", .data = OTX_PEM },
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{ .compatible = "marvell,pci-host-octeontx2-pem", .data = OTX2_PEM },
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{ }
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};
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U_BOOT_DRIVER(pci_octeontx) = {
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.name = "pci_octeontx",
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.id = UCLASS_PCI,
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.of_match = pci_octeontx_ids,
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.ops = &pci_octeontx_ops,
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.of_to_plat = pci_octeontx_of_to_plat,
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.probe = pci_octeontx_probe,
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.priv_auto = sizeof(struct octeontx_pci),
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.flags = DM_FLAG_PRE_RELOC,
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};
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